One chamber multi-station selective metal removal

Patent metadata

Field	Value
Publication number	US-12374568-B2
Application number	US-202318458146-A
Country	US
Kind code	B2
Filing date	Aug 29, 2023
Priority date	Aug 29, 2023
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

First claim

What is claimed is:

1. A method of selective metal removal via gradient oxidation for a gap-fill, the method comprising:
performing process cycles, each process cycle comprising:
placing a first wafer having a first semiconductor structure thereon into a first processing station, the first semiconductor structure comprising a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer;
performing a reduction process on the first wafer in the first processing station, reducing oxides from the seed layer on the bottom surface of the feature;
transferring the first wafer to a second processing station;
performing a gradient oxidation process on the first wafer in the second processing station, partially oxidizing the seed layer in a field region over the top surface of the dielectric layer;
transferring the first wafer to a third processing station;
performing a gradient etch process on the first wafer in the third processing station, removing the oxidized seed layer;
transferring the first wafer to a fourth processing station; and
performing the gradient etch process on the first wafer in the fourth processing station,
wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

2. The method of claim 1 , wherein the each process cycle further comprises:
when placing the first wafer in the first processing station, placing a second wafer having a second semiconductor structure thereon into the second processing station, a third wafer having a third semiconductor structure thereon into the third processing station, and a fourth wafer having a fourth semiconductor structure thereon into the fourth processing station, each of the second, third, and fourth semiconductor structures comprising a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer;
when performing the reduction process on the first wafer in the first processing station, performing:
the gradient oxidation process on the second wafer in the second processing station, if the reduction process has been performed on the second wafer; and
the gradient etch process on the third wafer in the third processing station and on the fourth wafer in the fourth processing station, if the gradient oxidation process has been performed on the third and fourth wafers;

when transferring the first wafer to the second processing station, transferring the second wafer to the third processing station, the third wafer to the fourth processing station, and the fourth wafer to the first processing station;
when performing the gradient oxidation process on the first wafer in the second processing station, performing:
the reduction process on the fourth wafer in the first processing station; and
the gradient etch process on the second wafer in the third processing station and the third wafer in the fourth processing station, if the gradient oxidation process has been performed on the second and third wafers;

when transferring the first wafer to the third processing station, transferring the second wafer to the fourth processing station, the third wafer to the first processing station, and the fourth wafer to the second processing station;
when performing the gradient etch process on the first wafer in the third processing station, performing:
the reduction process on the third wafer in the first processing station;
the gradient oxidation process on the fourth wafer in the second processing station; and
the gradient etch process on the second wafer in the fourth processing station, if the gradient oxidation process has been performed on the second wafer;

when transferring the first wafer to the fourth processing station, transferring the second wafer to the first processing station, the third wafer to the second processing station, and the fourth wafer to the third processing station;
when performing the gradient etch process on the first wafer in the fourth processing station, performing:
the reduction process on the second wafer in the first processing station;
the gradient oxidation process on the third wafer in the second processing station; and

the gradient etch process on the fourth wafer in the third processing station.

3. The method of claim 1 , wherein the reduction process comprises exposing the seed layer to a plasma formed from process gas including hydrogen (H 2 )-containing gas.

4. The method of claim 3 , wherein the reduction process is performed at a pressure between 2 m Torr and 120 mTorr and at a temperature of between 200° C. and 450° C. for a time duration of between 10 seconds and 90 seconds.

5. The method of claim 1 , wherein the gradient oxidation process comprises exposing the seed layer to a plasma formed from a process gas including oxygen (O 2 ).

6. The method of claim 5 , wherein the gradient oxidation process is performed at a pressure between 2 mTorr and 120 mTorr and at a temperature of between 200° C. and 450° C. for a time duration of between 10 seconds and 90 seconds.

7. The method of claim 1 , wherein the gradient etch process comprises soaking the seed layer in a precursor including at least one of tungsten chloride (WCl 5 , WCl 6 ), molybdenum fluoride (MoF 6 ), molybdenum chloride (MoCl 5 , MoCl 6 ), tungsten fluoride (WF 6 ), tantalum chloride (TaCl 5 ), and tantalum fluoride (TaF 5 ).

8. The method of claim 7 , wherein the gradient etch process is performed at a temperature of between 200° C. and 450° C. for a time duration of between 10 seconds and 90 seconds.

9. A method of selective metal removal via gradient oxidation for a gap-fill, the method comprising:
performing process cycles, each process cycle comprising:
placing a first wafer having a first semiconductor structure thereon into a first processing station, a second wafer having a second semiconductor structure thereon into a second processing station, a third wafer having a third semiconductor structure thereon into a third processing station, and a fourth wafer having a fourth semiconductor structure thereon into a fourth processing station, each of the first, second, third, and fourth semiconductor structures comprising a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer;
performing a reduction process on the first wafer in the first processing station and on the third wafer in the third processing station, reducing oxides from the seed layer on the bottom surface of the feature;
performing a gradient oxidation process on the first wafer in the first processing station and on the third wafer in the third processing station, partially oxidizing the seed layer in a field region over the top surface of the dielectric layer;
transferring the first wafer into the second processing station, the second wafer into the third processing station, the third wafer into the fourth processing station, and the fourth wafer into the first processing station;
performing:
a gradient etch process on the first wafer in the second processing station and on the third wafer in the fourth processing station, removing the oxidized seed layer; and
the reduction process on the second wafer in the third processing station and on the fourth wafer in the first processing station; and

performing:
the gradient etch process on the first wafer in the second processing station and on the third wafer in the fourth processing station; and
the gradient oxidation process on the second wafer

Assignees

• Applied Materials Inc

Inventors

• Yue Shiyu
• Patel Sahil Jaykumar
• Lei Yu
• Lei Wei
• Hsu Chih-Hsun
• Xu Yi
• Hairisha Abulaiti
• Trinh Cong
• Yang Yixiong
• Oh Ju Hyun
• Zhang Aixi
• Gao Xingyao
• Wang Rongjun

Classifications

• H10P50/269

  pre- or post-treatments, e.g. anti-corrosion processes · CPC title

• H10P50/267

  using plasmas · CPC title

• H10P72/0421 Primary

  for drying etching · CPC title

• H10P72/0468

  comprising a chamber adapted to a particular process · CPC title

• H01J37/32899 Primary

  Multiple chambers, e.g. cluster tools · CPC title