Capacitor devices with shared electrode and methods of fabrication

Patent metadata

Field	Value
Publication number	US-12369326-B1
Application number	US-202217657934-A
Country	US
Kind code	B1
Filing date	Apr 4, 2022
Priority date	Mar 15, 2022
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

First claim

What is claimed is:

1. A device comprising:
a conductive interconnect in a first level, the conductive interconnect comprising a first length along a first direction;
a second level above the first level, the second level comprising a plurality of electrode structures laterally spaced apart on the conductive interconnect along the first length, the plurality of electrode structures comprising a conductive hydrogen barrier material;
a third level above the second level, the third level comprising a plurality of plate electrodes, wherein individual ones of the plurality of plate electrodes are on individual ones of the plurality of electrode structures, and wherein the individual ones of the plurality of plate electrodes have a respective second length that extends along a second direction orthogonal to the first direction; and
a fourth level above the third level, the fourth level comprising:
a plurality of memory devices, wherein a first individual ones of the plurality of memory devices are on a first individual one of the plurality of plate electrodes, wherein an individual memory device is on a second individual one of the plurality of plate electrodes, wherein a second individual ones of the plurality of memory devices are on a third individual one of the plurality of plate electrodes, and wherein the individual ones of the plurality of memory devices comprise a perovskite material; and
an encapsulation layer on sidewalls of the first individual ones of the plurality of memory devices, on a sidewall of the individual memory device, and on sidewalls of the second individual ones of the plurality of memory devices.

2. The device of claim 1 , wherein the second individual one of the plurality of plate electrodes comprises a third length that is less than a fourth length of the first individual one of the plurality of plate electrodes or a fifth length of the third individual one of the plurality of plate electrodes.

3. The device of claim 1 , wherein the plurality of memory devices are planar capacitors comprising a bottom electrode, a dielectric layer comprising a perovskite material on the bottom electrode, and a top electrode on the dielectric layer.

4. The device of claim 1 , wherein the individual ones of the plurality of memory devices comprises a trench capacitor comprising a perovskite dielectric layer, wherein the trench capacitor comprises an annular structure comprising a central electrode surrounded by a dielectric layer, and wherein the dielectric layer is laterally surrounded by an outer electrode.

5. The device of claim 1 , wherein the individual ones of the plurality of plate electrodes extend beyond a perimeter of a respective individual ones of the plurality of electrode structures.

6. The device of claim 1 , wherein the individual ones of the plurality of plate electrodes comprise a first thickness under the individual ones of the plurality of memory devices and a second thickness away from the individual ones of the plurality of memory devices.

7. The device of claim 1 , wherein the individual ones of the plurality of electrode structures are directly below a respective memory device in the plurality of memory devices.

8. The device of claim 1 , wherein the perovskite material comprises:
bismuth ferrite (BFO) or BFO with a first doping material, where in the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric material which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ;
a hexagonal ferroelectric which includes one of: YMnO 3 , or LuFeO 3 ;
hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or their alloyed oxides;
hafnium oxides as Hf (1-x) E (x) O (y) , where E is one of Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively;
Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-x-y) Mg (x) Nb (y) N, wherein x and y are third and fourth fractions, respectively;
y doped HfO 2 ;
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate;
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100; or
a paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 , HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectrics.

9. A device, comprising:
a conductive interconnect in a first dielectric within a first level, the conductive interconnect comprising a first length along a first direction;
a second level above the first level, the second level comprising:
a plurality of electrode structures, wherein individual ones of the plurality of electrode structures are laterally spaced apart on the conductive interconnect along the first length, the individual ones of the plurality of electrode structures comprising a first conductive hydrogen barrier material; and
an etch stop layer laterally surrounding the individual ones of the plurality of electrode structures, wherein the etch stop layer is on the conductive interconnect and on the first dielectric;

a third level above the second level, the third level comprising a plurality of plate electrodes, wherein individual ones of the plurality of plate electrodes are on individual ones of the plurality of electrode structures, wherein the individual ones of the plurality of plate electrodes have a length that extend along a second direction orthogonal to the first direction; and
a fourth level above the third level, the fourth level comprising:
a plurality of memory devices, wherein a first individual ones of the plurality of memory devices are on a first individual one of the plurality of plate electrodes, wherein an individual memory device is on a second individual one of the plurality of plate electrodes, and wherein a second individual ones of the plurality of memory devices are on a third individual one of the plurality of plate electrodes;
an encapsulation layer on sidewalls of the first individual ones of the plurality of memory devices, on the first individual one of the plurality of plate electrodes, on sidewall of the individual memory device, on sidewalls of the second individual ones of the plurality of memory devices and on the third individual one of the plurality of plate electrodes, wherein the encapsulation layer is substantially aligned with sidewalls of the first individual one of the plurality of plate electrodes, with the second individual one of the plurality of plate electrodes, and with the third individual one of the plurality of plate electrodes;
a second dielectric on the encapsulation layer; and
a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on the individual ones of the plurality of memory devices, and wherein the individual ones of the plurality o

Assignees

• Kepler Computing Inc

Inventors

• Sato Noriyuki
• Gosavi Tanay
• Rios Rafael
• Mathuriya Amrita
• Mukherjee Niloy
• Manfrini Mauricio
• Dokania Rajeev Kumar
• Rathi Somilkumar J
• Manipatruni Sasikanth

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/711

  having non-planar surfaces, e.g. formed by texturisation · CPC title

• H10N79/00

  Integrated devices, or assemblies of multiple devices, comprising at least one solid-state element covered by group H10N70/00 (ReRAM devices H10B63/00; PCRAM devices H10B63/10) · CPC title