Apparatuses including interconnect structures including dielectric material surrounded by conductive material, and related memory devices

Patent metadata

Field	Value
Publication number	US-12368101-B2
Application number	US-202418652551-A
Country	US
Kind code	B2
Filing date	May 1, 2024
Priority date	Dec 3, 2019
Publication date	Jul 22, 2025
Grant date	Jul 22, 2025

Abstract

An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
interconnect structures comprising conductive material extending through insulative material;
dielectric material adjacent to the interconnect structures, the conductive material adjacent to and at least partially surrounding the dielectric material; and
one or more air gaps laterally intervening between portions of the conductive material of individual interconnect structures.

2. The apparatus of claim 1 , wherein the dielectric material comprises a nitride cap material adjacent to the one or more air gaps, a material composition of the nitride cap material differing from a material composition of the insulative material.

3. The apparatus of claim 1 , wherein an additional portion of the conductive material underlies the one or more air gaps.

4. The apparatus of claim 1 , wherein the conductive material comprises a single material substantially surrounding the one or more air gaps.

5. The apparatus of claim 1 , wherein the dielectric material directly physically contacts the conductive material.

6. The apparatus of claim 1 , wherein the interconnect structures are located within through-array vias extending substantially through an entirety of the insulative material, at least some of the interconnect structures comprising an aspect ratio of at least about 100:1.

7. The apparatus of claim 1 , further comprising conductive structures in vertical alignment with each of the interconnect structures, the dielectric material, and the one or more air gaps.

8. A memory device, comprising:
a conductive pad underlying insulative material;
a conductive structure overlying the insulative material;
dielectric material vertically intervening between the conductive pad and the conductive structure; and
a conductive contact comprising conductive material vertically extending between the conductive pad and the conductive structure, the conductive material laterally adjacent to and substantially surrounding the dielectric material.

9. The memory device of claim 8 , wherein the memory device comprises a memory array region and a staircase region adjacent to the memory array region, multiple conductive contacts extending within one or more of the staircase region and the memory array region.

10. The memory device of claim 8 , wherein the conductive contact exhibits a substantially circular cross-sectional shape, the dielectric material substantially filling a central region of the conductive contact.

11. The memory device of claim 8 , further comprising opposing portions of barrier material adjacent to the conductive material, a thickness of the conductive material relatively greater than individual thicknesses of the opposing portions of the barrier material.

12. The memory device of claim 8 , wherein outer lateral boundaries of the conductive structure are substantially aligned with outer lateral boundaries of the conductive material of the conductive contact.

13. The memory device of claim 8 , wherein a thickness of the dielectric material is relatively greater than a thickness of the conductive material of the conductive contact.

14. The memory device of claim 8 , wherein the memory device comprises an array of memory cells in vertical alignment with a control device comprising complementary metal oxide semiconductor (CMOS) circuitry, the conductive contact operably coupled with the CMOS circuitry.

15. A NAND Flash memory device, comprising:
interconnect structures vertically extending through insulative material; and
trenches horizontally extending between at last some of the interconnect structures, the trenches comprising:
conductive material adjacent to the insulative material; and
dielectric material within central regions of the trenches, the dielectric material adjacent to and at least partially surrounded by the conductive material.

16. The NAND Flash memory device of claim 15 , wherein the conductive material laterally intervenes between the dielectric material and the insulative material, a thickness of the conductive material substantially uniform along a length of the trenches.

17. The NAND Flash memory device of claim 15 , further comprising additional portions of the dielectric material within central regions of at least some of the interconnect structures.

18. The NAND Flash memory device of claim 17 , wherein a thickness of the additional portions of the dielectric material within the interconnect structures is relatively greater than a thickness of the dielectric material within the trenches.

19. The NAND Flash memory device of claim 15 , further comprising a barrier material within the trenches, the barrier material adjacent to and at least partially surrounding the conductive material.

20. The NAND Flash memory device of claim 15 , further comprising a dielectric liner material laterally intervening between the insulative material and the conductive material, wherein the insulative material comprises a stack structure comprising vertically alternating insulative structures and conductive structures arranged in tiers, each of the tiers individually comprising one of the insulative structures and one of the conductive structures.

Assignees

• Lodestar Licensing Group Llc
• Battelle Energy Alliance Llc

Inventors

• Greenlee Jordan D
• Xu Lifang
• Klein Rita J
• Li Xiao
• Mcteer Everett A

Classifications

• H10W42/121

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/035

  combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers · CPC title

• H10W72/244

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title