Enhanced capture pads for through semiconductor vias

Patent metadata

Field	Value
Publication number	US-9040418-B2
Application number	US-201314076233-A
Country	US
Kind code	B2
Filing date	Nov 10, 2013
Priority date	Nov 7, 2012
Publication date	May 26, 2015
Grant date	May 26, 2015

Abstract

Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.

First claim

What is claimed is:

1. A method of forming a capture pad on a semiconductor substrate comprising:
providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled through silicon vias (TSVs) extending between the active side and the inactive side;
filling the TSVs with a metal;
defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; and
filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion devoid of the insulator islands that follows an outline of each of the TSVs and a mixed portion comprising insulator islands dispersed in the metal.

2. The method of claim 1 wherein each of the capture pads have a first portion in direct contact with the TSVs and a second portion away from the TSVs and in direct contact with the first portion, the all metal portion being only in the second portion of each of the capture pads.

3. The method of claim 1 wherein each of the capture pads have a first portion in direct contact with the TSVs and a second portion away from the TSVs and in direct contact with the first portion, the all metal portion being in the first and second portions of each of the capture pads so as to extend entirely through each of the capture pads.

4. The method of claim 1 wherein the step of filling comprises filling the TSVs only partially with the metal so that the TSVs are recessed with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs.

5. The method of claim 1 wherein the step of filling comprises filling the TSVs fully with the metal, further comprising etching to recess the TSVs with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs.

6. The method of claim 1 further comprising forming at least one additional layer of material directly on the capture pads.

7. The method of claim 1 wherein the capture pad is on the active side of the semiconductor substrate.

8. The method of claim 1 wherein the capture pad is on the inactive side of the semiconductor substrate.

9. The method of claim 1 wherein the metal comprises copper.

10. The method of claim 1 further comprising joining the semiconductor substrate to at least one other semiconductor substrate to form a 3-dimensional semiconductor structure.

11. A method of forming a capture pad on a semiconductor substrate comprising:
providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled through silicon vias (TSVs) extending between the active side and the inactive side;
filling the TSVs with a metal;
defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; and
filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having a TSV outline portion that follows an outline of each of the TSVs, at least part of each of the TSV outline portions being an all metal portion that follows the outline of each of the TSVs.

12. The method of claim 11 wherein the TSV outline portions have a first portion in direct contact with each of the TSVs and a second portion away from each of the TSVs and in direct contact with the first portion, the all metal portion being only in the second portion of each of the capture pads, the first and second portions being an entire thickness of each of the capture pads.

13. The method of claim 11 wherein the TSV outline portions have a first portion in direct contact with each of the TSVs and a second portion away from each of the TSVs and in direct contact with the first portion, the all metal portion being in the first and second portions of each of the capture pads so as to extend entirely through each of the capture pads.

14. The method of claim 11 wherein the step of filling comprises filling the TSVs only partially with the metal so that the TSVs are recessed with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs.

15. The method of claim 11 wherein the step of filling comprises filling the TSVs fully with the metal, further comprising etching to recess the TSVs with respect to the at least one of the active side and the inactive side and wherein the step of filling the open areas includes filling the recessed TSVs.

16. The method of claim 11 further comprising forming at least one additional layer of material directly on the capture pads.

17. The method of claim 11 wherein the capture pad is on the active side of the semiconductor substrate.

18. The method of claim 11 wherein the capture pad is on the inactive side of the semiconductor substrate.

19. The method of claim 11 wherein the metal comprises copper.

Assignees

• IBM

Inventors

• Farooq Mukta G
• Griesemer John A
• Lafontant Gary
• Petrarca Kevin S
• Volant Richard P

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/856

  Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15) · CPC title

• H10W72/953

  not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title