Methods to improve magnetic tunnel junction memory cells by treating native oxide

Patent metadata

Field	Value
Publication number	US-12364165-B2
Application number	US-202318501843-A
Country	US
Kind code	B2
Filing date	Nov 3, 2023
Priority date	Oct 31, 2018
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Methods of forming magnetic tunnel junction (MTJ) memory cells used in a magneto-resistive random access memory (MRAM) array are provided. A pre-clean process is performed to remove a metal oxide layer that may form on the top surface of the bottom electrodes of MTJ memory cells during the time the bottom electrode can be exposed to air prior to depositing MTJ layers. The pre-clean processes may include a remote plasma process wherein the metal oxide reacts with hydrogen radicals generated in the remote plasma.

First claim

What is claimed is:

1. A method, the method comprising:
forming a bottom electrode via in a dielectric stack;
forming a bottom electrode layer over the bottom electrode via and the dielectric stack, the bottom electrode layer comprising a plurality of conductive layers;
reducing an oxide layer over the bottom electrode layer, wherein reducing the oxide layer exposes a conductive surface;
after reducing the oxide layer, forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
forming a top electrode layer over the MTJ layer;
patterning the top electrode layer, the MTJ layer, and the bottom electrode layer to form a magnetic random access memory (MRAM) cell, wherein patterning comprises recessing the dielectric stack;
forming a dielectric spacer layer over the MRAM cell, the dielectric spacer layer physically contacting a sidewall of the patterned top electrode layer;
etching the dielectric spacer layer to form dielectric spacers; and
forming a protective dielectric layer over the MRAM cell, the protective dielectric layer physically contacting the sidewall of the patterned top electrode layer.

2. The method of claim 1 , wherein reducing the oxide layer comprises producing a gaseous byproduct.

3. The method of claim 1 , wherein etching the dielectric spacer layer comprises exposing a portion of the sidewall of the patterned top electrode layer.

4. The method of claim 1 , wherein the MTJ layer comprises a tunnel barrier layer interposed between a pinning layer and a free layer.

5. The method of claim 1 , wherein the dielectric stack comprises:
a silicon oxide layer over an etch stop layer; and
an anti-reflective coating over the silicon oxide layer.

6. The method of claim 5 , wherein recessing the dielectric stack comprises:
patterning the anti-reflective coating; and
patterning a portion of the silicon oxide layer.

7. The method of claim 1 , wherein the top electrode layer comprises:
a first conductive layer;
a second conductive layer over the first conductive layer, the second conductive layer being different from the first conductive layer; and
a third conductive layer over the second conductive layer, the third conductive layer being different from the first conductive layer and the second conductive layer.

8. The method of claim 7 , wherein patterning the top electrode layer comprises patterning the second conductive layer, and wherein the patterned second conductive layer physically contacts the dielectric spacers and the protective dielectric layer.

9. A method, comprising:
forming a bottom electrode layer over a dielectric stack, wherein a native oxide film forms over a top surface of the bottom electrode layer;
performing a treatment to chemically reduce the native oxide film;

after performing the treatment, forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer;
forming a top electrode layer over the MTJ layer;
forming a silicon-containing layer over the top electrode layer;
patterning the silicon-containing layer, the top electrode layer, the MTJ layer, and the bottom electrode layer;
after patterning, forming a dielectric spacer layer over and physically contacting the patterned top electrode layer, the patterned MTJ layer, and the patterned bottom electrode layer;
etching the dielectric spacer layer to form dielectric spacers, the etching exposing a portion of a sidewall of the patterned top electrode layer;
forming a protective dielectric layer over the dielectric spacers; and
depositing a dielectric fill layer over the protective dielectric layer.

10. The method of claim 9 , wherein before performing the treatment, the top surface of the bottom electrode layer comprises TiO x N y or TiO 2 .

11. The method of claim 10 , wherein the treatment comprises a thermal treatment with H 2 or NH 3 .

12. The method of claim 10 , wherein the treatment comprises a plasma treatment with hydrogen radicals.

13. The method of claim 9 , further comprising forming a bottom electrode via in the dielectric stack, wherein the bottom electrode is formed over the bottom electrode via.

14. The method of claim 9 , further comprising planarizing the dielectric fill layer to be level with the protective dielectric layer and the patterned top electrode layer.

15. A method, comprising:
forming a bottom electrode layer over a dielectric stack, the bottom electrode layer comprising:
a first metal nitride layer; and
a second metal nitride layer over the first metal nitride layer, wherein a metal oxide layer is disposed over the second metal nitride layer;

performing a reduction treatment on the metal oxide layer;
forming a magnetic tunnel junction (MTJ) layer over the second metal nitride layer;
forming a top electrode layer over the MTJ layer;
forming a mask layer over the top electrode layer;
patterning the mask layer, the top electrode layer, the MTJ layer, the bottom electrode layer, and a portion of the dielectric stack;
depositing a first dielectric layer along the patterned dielectric stack, the patterned bottom electrode layer, the patterned MTJ layer, the patterned top electrode layer, and the patterned mask layer;
etching the first dielectric layer to form dielectric spacers; and
conformally depositing a second dielectric layer along an upper surface of the patterned dielectric stack, the dielectric spacers, a sidewall of the patterned top electrode layer, and the patterned mask layer.

16. The method of claim 15 , wherein the top electrode layer comprises:
a third metal nitride layer over the MTJ layer;
a metal layer over the first metal nitride layer; and
a fourth metal nitride layer over the metal layer, and wherein patterning the top electrode layer comprises patterning the third metal nitride layer, the metal layer, and the fourth metal nitride layer.

17. The method of claim 16 , wherein etching the first dielectric layer comprises:
exposing an entirety of a sidewall of the patterned fourth metal nitride layer; and
exposing a portion of a sidewall of the patterned metal layer.

18. The method of claim 16 , wherein a metal of the third metal nitride layer is different from a metal of the fourth metal nitride layer.

19. The method of claim 16 , wherein patterning the top electrode layer comprises patterning the metal layer, and wherein the patterned metal layer is in physical contact with the dielectric spacers and the second dielectric layer.

20. The method of claim 15 , wherein performing the reduction treatment on the metal oxide layer comprises using at least one of hydrogen or nitrogen.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Jung-Tang
• Wu meng yu
• Wu Szu-Hua
• Lee Chin-Szu

Classifications

• H10N50/85

  Materials of the active region · CPC title

• H10N50/80

  Constructional details · CPC title

• H10N50/10 Primary

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• H10N50/01 Primary

  Manufacture or treatment · CPC title