Semiconductor devices and data storage systems including the same

Patent metadata

Field	Value
Publication number	US-12363899-B2
Application number	US-202217743738-A
Country	US
Kind code	B2
Filing date	May 13, 2022
Priority date	Jun 10, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extending by different lengths in a second direction on the second region to have pad regions in which upper surfaces thereof are exposed, channel structures penetrating the gate electrodes, extending in the first direction, and respectively including a channel layer, on the first region, contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction, and contact insulating layers surrounding the contact plugs. The gate electrodes have side surfaces protruding further toward the contact plugs in the pad regions than ones of the gate electrodes therebelow.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first semiconductor structure comprising a first substrate, circuit devices on the first substrate, and lower interconnection lines; and
a second semiconductor structure on the first semiconductor structure,
wherein the second semiconductor structure comprises:
a second substrate comprising a first region and a second region;
gate electrodes and interlayer insulating layers alternately stacked in a first direction perpendicular to an upper surface of the second substrate, the gate electrodes extending by different lengths in a second direction on the second region to provide pad regions comprising upper surfaces that are exposed by the interlayer insulating layers;
channel structures penetrating the gate electrodes, extending in the first direction, and each comprising a channel layer, on the first region;
respective contact plugs electrically connected to the pad regions of the gate electrodes, penetrating the gate electrodes, and extending in the first direction; and
contact insulating layers surrounding the respective contact plugs,
wherein the pad regions comprise first and second pad portions, the first pad portions protruding further toward the respective contact plugs than ones of the gate electrodes therebelow to overlap the respective contact plugs in the first direction, and
wherein the gate electrodes have a first thickness on the first region, and the second pad portions have a second thickness greater than the first thickness.

2. The semiconductor device of claim 1 , wherein the first pad portions have a third thickness smaller than the second thickness.

3. The semiconductor device of claim 1 , wherein the respective contact plugs are in contact with upper surfaces and side surfaces of the first pad portions.

4. The semiconductor device of claim 1 , wherein the respective contact plugs have a first width on the pad regions and have a second width smaller than the first width below the pad regions.

5. The semiconductor device of claim 1 , wherein the contact insulating layers extend in the first direction between the gate electrodes and the respective contact plugs, and comprise bent portions that protrude toward the respective contact plugs along lower surfaces of the first pad portions.

6. The semiconductor device of claim 1 ,
wherein the contact insulating layers comprise lower contact insulating layers below the pad regions and upper contact insulating layers on the pad regions, and
wherein the lower contact insulating layers and the upper contact insulating layers are spaced apart from each other.

7. The semiconductor device of claim 1 , wherein the second thickness is greater than a maximum gate thickness among the gate electrodes on the first region.

8. The semiconductor device of claim 1 ,
wherein the second semiconductor structure further comprises gate dielectric layers extending along upper and lower surfaces of the gate electrodes, and
wherein upper surfaces of the first pad portions are exposed by the gate dielectric layers.

9. The semiconductor device of claim 8 , wherein side surfaces of the ones of the gate electrodes below the pad regions are in contact with the contact insulating layer without the gate dielectric layers therebetween.

10. The semiconductor device of claim 1 , wherein the second semiconductor structure further comprises:
sacrificial insulating layers in contact with the gate electrodes and alternately stacked with the interlayer insulating layers in a region in which the second substrate is not disposed;
a through via penetrating the sacrificial insulating layers and the interlayer insulating layers, extending into the first semiconductor structure, and comprising a same material as the contact plugs; and
a via insulating layer surrounding the through via.

11. The semiconductor device of claim 10 , wherein side surfaces of the sacrificial insulating layers protrude further than side surfaces of the interlayer insulating layers toward the through via.

12. The semiconductor device of claim 1 , wherein the respective contact plugs extend into the first semiconductor structure.

13. The semiconductor device of claim 1 ,
wherein the second semiconductor structure further comprises a substrate insulating layer penetrating the second substrate, and
wherein lower ends of the contact plugs are in the substrate insulating layer.

14. The semiconductor device of claim 1 , wherein the second semiconductor structure further comprises:
a first horizontal conductive layer below the gate electrodes on the first region;
a horizontal insulating layer below the gate electrodes on the second region; and
a second horizontal conductive layer on the first horizontal conductive layer and the horizontal insulating layer.

15. A semiconductor device, comprising:
a substrate comprising a first region and a second region;
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, and extending by different lengths in a second direction on the second region to provide pad regions comprising upper surfaces that are exposed;
channel structures penetrating the gate electrodes, extending in the first direction, and each comprising a channel layer, on the first region;
respective contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction; and
contact insulating layers surrounding the respective contact plugs,
wherein the gate electrodes comprise side surfaces protruding further toward the respective contact plugs in the pad regions than ones of the gate electrodes therebelow.

16. The semiconductor device of claim 15 ,
wherein the pad regions comprise first pad portions having the protruding side surfaces and upper surfaces in contact with the contact plugs, and second pad portions surrounding the first pad portions, and
wherein the first pad portions have a first thickness, and the second pad portions have a second thickness greater than the first thickness.

17. The semiconductor device of claim 16 , further comprising:
gate dielectric layers extending along upper surfaces and lower surfaces of the gate electrodes,
wherein the gate dielectric layers extend to upper surfaces and lower surfaces of the second pad portions, and wherein upper surfaces and lower surfaces of the first pad portions are free of the gate dielectric layers.

18. The semiconductor device of claim 15 , wherein the gate electrodes below the pad regions are spaced apart from the contact plugs by the contact insulating layers.

19. A data storage system, comprising:
a semiconductor storage device comprising a substrate comprising a first region and a second region, circuit devices on one side of the substrate, and input/output pads electrically connected to the circuit devices; and
a controller electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device,
wherein the semiconductor storage device comprises:
gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, and extending by different lengths in a second direction on the second region to provide pad regions comprising upper surfaces that are exposed;
channel structures penetrating the gate electrodes, extending in the first direction, and each comprising a channel layer, on the first region;
respective contact plugs penetrating

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Yonghoon
• Kim Junhyoung
• Lim Joonsung

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title