Semiconductor storage device

Patent metadata

Field	Value
Publication number	US-11672113-B2
Application number	US-202017007675-A
Country	US
Kind code	B2
Filing date	Aug 31, 2020
Priority date	Nov 26, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A semiconductor storage device includes a substrate having a surface, a first conductive layer 25 disposed on a substrate and extending in an X direction parallel to the surface of the substrate; a second conductive layer 25 that disposed on the first conductive layer 25 and extending in the X direction; an insulation plug 30 disposed on the substrate, extends in a Z direction intersecting with the X direction, and intersects with the first conductive layer 25; and a contact plug CC disposed on the first insulation plug 30, extends in the Z direction, and intersects with the second conductive layer 25.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a substrate having a surface;
a first conductive layer disposed on the substrate, the first conductive layer extending in a first direction parallel to the surface of the substrate, the first conductive layer having a hole extending through the first conductive layer;
a second conductive layer disposed on over the first conductive layer, and extending in the first direction;
a first insulating layer disposed between the first conductive layer and the second conductive layer,
a first insulation plug disposed on the substrate, the first insulation plug extending in a second direction intersecting with the first direction, the first insulation plug extending through the hole of the first conductive layer; and
a contact plug disposed on the first insulation plug, the contact plug extending in the second direction, and intersecting with the second conductive layer,
wherein a first width of the hole of the first conductive layer in the first direction is substantially the same as a second width of the first insulation plug at the first insulating layer in the first direction,
wherein a corner between the hole and an upper surface of the second conductive layer is covered with a second insulating layer.

2. The semiconductor storage device according to claim 1 , wherein the contact plug contacts a side surface of the second conductive layer in an area in which the contact plug intersects with the second conductive layer, whereby the contact plug is electrically connected to the second conductive layer.

3. The semiconductor storage device according to claim 1 , wherein
a first cross section is a cross section of a first portion of the contact plug intersects with the second conductive layer along the first direction,
a second cross section is a cross section of a second portion of the contact plug above the second conductive layer along the first direction, and
a diameter of the first cross section is greater than a diameter of the second cross section.

4. The semiconductor storage device according to claim 1 ,
wherein the contact plug contacts a side surface of the second conductive layer and extends to the first insulating layer.

5. The semiconductor storage device according to claim 1 , further comprising:
a second insulation plug disposed on the substrate, the second insulation plug extending in the second direction, and intersecting with the first conductive layer; and
a second insulating layer disposed on the second insulation plug.

6. The semiconductor storage device according to claim 5 ,
wherein the second insulation plug is disposed around the first insulation plug, and
wherein a distance from a surface of the substrate to an upper surface of the second insulation plug is a same as a distance from the surface of the substrate to an upper surface of the first insulation plug.

7. The semiconductor storage device according to claim 1 , further comprising
a conductive pillar disposed on the substrate, the conductive pillar extending in the second direction, and intersecting with the first and second conductive layers,
wherein a portion where the conductive pillar intersects with the first conductive layer, and a portion where the conductive pillar intersects with the second conductive layer, each function as a memory cell transistor.

8. The semiconductor storage device according to claim 1 , wherein in an area where the first insulation plug and the contact plug come into contact with each other, the first insulation plug having: (a) a first portion having a surface along the first direction, and (b) a second portion extending from the first portion in the second direction and extending into the contact plug.

9. The semiconductor storage device according to claim 1 , wherein in an area where the first insulation plug and the contact plug come into contact with each other, the contact plug has: (a) a first portion having a surface along the first direction, and (b) a second portion extending from the first portion in the second direction and extending to an outer peripheral portion of the first insulation plug.

10. The semiconductor storage device according to claim 1 , wherein the insulation plug is arranged as a support column.

11. The semiconductor storage device according to claim 1 , wherein the contact plug includes a plurality of conductive layers.

12. The semiconductor storage device according to claim 11 , wherein each of the plurality of conductive layers include a barrier metal.

13. The semiconductor storage device according to claim 11 , wherein the plurality of conductive layers include tungsten and titanium nitride.

14. The semiconductor storage device according to claim 11 , wherein the first conductive layer is a part of a stack of alternating conducting and insulating layers.

15. The semiconductor storage device according to claim 1 , wherein a lower surface of the contact plug is higher than a lower surface of the second conductive layer in the second direction.

16. A semiconductor storage device comprising:
a first insulation plug disposed on a substrate and extending in a first direction intersecting with a surface of the substrate;
a contact plug disposed on the first insulation plug and extending in the first direction;
a first conductive layer arranged on the substrate around the first insulation plug and extending in a second direction parallel to the surface of the substrate, the first conductive layer having a hole extending through the first conductive layer;
a second conductive layer arranged around the contact plug on the first conductive layer and extending in the second direction; and
a first insulating layer disposed between the first conductive layer and the second conductive layer,
wherein a first width of the first insulation plug at the first conductive layer in the second direction is substantially the same as a second width of the first insulation plug at the first insulating layer in the second direction,
wherein a corner between the hole and an upper surface of the second conductive layer is covered with a second insulating layer.

17. The semiconductor storage device according to claim 16 , wherein the contact plug contacts a side surface of the second conductive layer in an area in which the contact plug intersects with the second conductive layer, whereby the contact plug is electrically connected to the second conductive layer.

18. The semiconductor storage device according to claim 16 ,
wherein the contact plug contacts a side surface of the second conductive layer and extends to the first insulating layer.

19. The semiconductor storage device according to claim 16 , further comprising
a conductive pillar disposed on the substrate, the conductive pillar extending in the first direction, and intersecting with the first and second conductive layers,
wherein a portion where the conductive pillar intersects with the first conductive layer, and a portion where the conductive pillar intersects with the second conductive layer, each function as a memory cell transistor.

Assignees

• Kioxia Corp

Inventors

• Kato Kaihei
• Fukushima Takashi
• Suzuki Kazutaka

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title