Barrier free interface between BEOL interconnects

Patent metadata

Field	Value
Publication number	US-12362235-B2
Application number	US-202318318917-A
Country	US
Kind code	B2
Filing date	May 17, 2023
Priority date	Apr 27, 2020
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

The present disclosure relates a method of forming an integrated chip. The method includes forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate, and forming a second ILD layer over the first ILD layer. The second ILD layer is patterned to form an interconnect opening that exposes the first interconnect. A blocking layer is formed onto the first interconnect. A barrier layer is formed within the interconnect opening and the blocking layer is removed to expose the first interconnect. A second interconnect is formed within the interconnect opening.

First claim

What is claimed is:

1. A method of forming an integrated chip, comprising:
forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
forming a second ILD layer over the first ILD layer;
patterning the second ILD layer to form an interconnect opening that exposes the first interconnect;
forming a blocking layer onto the first interconnect;
forming a barrier layer within the interconnect opening, wherein a part of the first ILD layer is exposed laterally between the blocking layer and the second ILD layer before forming the barrier layer;
removing the blocking layer to expose the first interconnect; and
forming a second interconnect within the interconnect opening.

2. The method of claim 1 , wherein an entirety of the blocking layer is confined directly above the first interconnect.

3. The method of claim 1 , further comprising:
forming an etch stop layer onto the first ILD layer; and
forming the second ILD layer onto the etch stop layer, wherein the blocking layer is laterally separated from the etch stop layer by non-zero spaces.

4. The method of claim 1 , wherein the blocking layer is a self-assembled monolayer.

5. The method of claim 1 ,
wherein the blocking layer is formed prior to forming the barrier layer; and
wherein the blocking layer is removed after forming the barrier layer.

6. A method of forming an integrated chip, comprising:
forming a conductor on a substrate;
forming a dielectric over the conductor;
etching the dielectric to form an interconnect opening that exposes the conductor;
forming a blocking layer onto the conductor;
forming a barrier layer within the interconnect opening, wherein the barrier layer is formed using an atomic layer deposition process that introduces a first precursor gas into a processing chamber and subsequently introduces a second precursor gas into the processing chamber, wherein the first precursor gas is not configured to adhere to the blocking layer;
removing the blocking layer to form an aperture extending through the barrier layer to the conductor; and
forming an interconnect within the interconnect opening and the aperture.

7. The method of claim 6 , wherein the blocking layer comprises an organic material.

8. The method of claim 6 , wherein the blocking layer is a silane or a thiolate.

9. The method of claim 6 , wherein the blocking layer has a smaller width than the interconnect opening.

10. An integrated chip, comprising:
a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate;
a barrier layer disposed within the ILD structure;
a second interconnect disposed on the barrier layer and extending through the barrier layer to the first interconnect, wherein a bottommost surface of the barrier layer vertically contacts an upper surface of the ILD structure and laterally extends past an interior sidewall of the barrier layer that faces the second interconnect;
wherein the second interconnect comprises a first conductive liner on the barrier layer, a second conductive liner on the first conductive liner, and a conductive core surrounded by the second conductive liner, the second conductive liner comprising a different material than the conductive core; and
wherein the barrier layer comprises tantalum nitride, the first conductive liner comprises ruthenium, the second conductive liner comprises cobalt, and the conductive core comprises copper.

11. The integrated chip of claim 10 , wherein the ILD structure comprises a first ILD layer surrounding the first interconnect and a second ILD layer surrounding the second interconnect, an upper surface of the first ILD layer being arranged laterally between an outer sidewall of the first interconnect and an interior sidewall of the second ILD layer.

12. The integrated chip of claim 10 , wherein the first interconnect comprises a conductive material contacting lower sidewalls of the ILD structure, the second interconnect having a bottom surface that is completely confined over the conductive material.

13. The integrated chip of claim 10 , wherein the barrier layer is completely laterally outside of the first interconnect.

14. The integrated chip of claim 10 , wherein the second interconnect comprises a curved lower surface facing the first interconnect.

15. The integrated chip of claim 10 , wherein the barrier layer comprises a vertically extending segment and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment, the horizontally extending segment having different heights at different lateral positions.

16. The integrated chip of claim 10 , further comprising:
a metal capping layer physically contacting a top of the second interconnect, wherein a top surface of the barrier layer is laterally outside of the metal capping layer and vertically below a lower surface of the metal capping layer facing the top of the second interconnect, and wherein the metal capping layer and the second conductive liner are a same material.

17. The integrated chip of claim 10 , wherein the first interconnect and the first conductive liner are a same material.

18. The integrated chip of claim 10 ,
wherein a metal capping layer physically contacts tops of the conductive core and the second conductive liner, a top surface of the barrier layer being laterally outside of the metal capping layer and vertically below a lower surface of the metal capping layer facing the top of the conductive core.

19. The integrated chip of claim 10 , wherein the barrier layer is substantially symmetric about a line bisecting the second interconnect.

20. The integrated chip of claim 10 , wherein the bottommost surface of the barrier layer vertically contacts the upper surface of the ILD structure along opposing sides of the first interconnect.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hsueh Hsiu-Wen
• Chen Chii-Ping
• Huang Po-Hsiang
• Tseng Ya-Ching

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/037

  the barrier, adhesion or liner layers being on top of a main fill metal · CPC title