Semiconductor device having a uniform and thin silicide layer on an epitaxial source/drain structure

Patent metadata

Field	Value
Publication number	US-12362187-B2
Application number	US-202017074110-A
Country	US
Kind code	B2
Filing date	Oct 19, 2020
Priority date	Jan 14, 2016
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

First claim

What is claimed is:

1. A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;
a gate structure disposed over parts of the fin structure, the gate structure extending in a second direction crossing the first direction; and
a source/drain epitaxial layer formed on the upper portion of the fin structure, which is not covered by the gate structure, wherein:
an upper portion of the source/drain epitaxial layer has a rhombus shape having a largest width,
a silicide layer is formed on a surface of the upper portion of the source/drain epitaxial layer that extends above and below a portion of the upper portion of the source/drain epitaxial layer having the largest width,
a source/drain contact is disposed on the silicide layer, and
a bottommost portion of the source/drain contact, which is closest to the substrate along a third direction normal to an upper surface of the substrate, wherein the third direction is perpendicular to the first direction and the second direction, is located closer to the substrate along the third direction than a bottommost portion of the silicide layer, which is closest to the substrate along the third direction normal to the upper surface of the substrate.

2. The semiconductor device of claim 1 , wherein the silicide layer has a substantially uniform thickness that is in a range from 1 nm to 10 nm.

3. The semiconductor device of claim 1 , wherein the silicide layer includes TiSi.

4. The semiconductor device of claim 1 , wherein the source/drain contact covers the silicide layer.

5. The semiconductor device of claim 4 , wherein the source/drain contact includes a first layer made of TiN or TaN and a second layer made of Co.

6. The semiconductor device of claim 5 , wherein a first liner layer is in direct contact with and covers the silicide layer.

7. The semiconductor device of claim 1 , wherein a fin liner layer is disposed on a lower portion of the source/drain epitaxial layer and on an upper surface of the isolation insulating layer.

8. The semiconductor device of claim 7 , wherein the silicide layer is in direct contact with the fin liner layer.

9. A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;
a gate structure disposed over parts of the fin structure, the gate structure extending in a second direction crossing the first direction;
a source/drain epitaxial layer formed on the upper portion of the fin structure, which is not covered by the gate structure;
an interlayer dielectric layer disposed over the isolation insulating layer; and
a source/drain contact, wherein:
an upper portion of the source/drain epitaxial layer has a rhombus shape having a top, a first side corner and a second side corner both located below the top and located above a bottom of the source/drain contact, and
a silicide layer is formed on the upper portion of the source/drain epitaxial layer covering the top and the first side corner but not covering the second side corner.

10. The semiconductor device of claim 9 , wherein the source/drain contact is in contact with the silicide layer disposed on the first side corner, and the second side corner is covered by an insulating layer.

11. The semiconductor device of claim 10 , wherein:
the source/drain contact includes a first layer, a second layer in contact with the silicide layer, and third layer disposed on the second layer, and
the first layer is disposed between the second layer and the interlayer dielectric layer.

12. The semiconductor device of claim 11 , wherein the first layer is made of Ti and the second layer is made of TiN or TaN.

13. A semiconductor device comprising:
an isolation insulating layer disposed over a substrate;
a fin structure disposed over the substrate, and extending in a first direction in plan view, an upper portion of the fin structure being exposed from the isolation insulating layer;
a gate structure disposed over parts of the fin structure, the gate structure extending in a second direction crossing the first direction;
a source/drain epitaxial layer formed on the upper portion of the fin structure, which is not covered by the gate structure;
an interlayer dielectric layer disposed over the isolation insulating layer; and
a source/drain contact, wherein:
an upper portion of the source/drain epitaxial layer has a rhombus shape including a top, a first side corner and a second side corner both located below the top, a distance between the first side corner and the second side corner corresponds to a largest width of the rhombus shape along a direction parallel to an upper surface of the substrate,
a silicide layer is formed on the upper portion of the source/drain epitaxial layer covering the top, the first side corner and a part of the upper portion of the source/drain epitaxial layer between the top and the second side corner, and
the source/drain contact is in contact with the silicide layer disposed on the first side corner, and the second side corner is covered by an insulating layer in direct contact with the second side corner.

14. The semiconductor device of claim 13 , wherein the insulating layer is disposed between the second side corner and the interlayer dielectric layer.

15. The semiconductor device of claim 13 , wherein the source/drain contact is in contact with the interlayer dielectric layer.

16. The semiconductor device of claim 13 , wherein the source/drain contact includes a Co layer.

17. The semiconductor device of claim 13 , wherein the silicide layer includes TiSi.

18. The semiconductor device of claim 13 , wherein a fin liner layer is disposed on a lower portion of the source/drain epitaxial layer and on an upper surface of the isolation insulating layer.

19. The semiconductor device of claim 18 , wherein the silicide layer is in direct contact with the fin liner layer.

20. The semiconductor device of claim 19 , wherein:
the fin liner layer in contact with the silicide layer covering the first side corner is in contact with the source/drain contact, and
the fin liner layer is in contact with the insulating layer covering the second side corner.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• LEE Kai-Hsuan
• Sheu Jyh-Cherng
• Wang Sung-Li
• Yang Cheng-Yu
• Wang Sheng-Chen
• Yeong Sai-Hooi

Classifications

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/066

  by forming silicides of refractory metals · CPC title

• H10D64/0112 Primary

  using conductive layers comprising silicides · CPC title