FinFETs with Low Source/Drain Contact Resistance

Patent metadata

Field	Value
Publication number	US-2020328291-A1
Application number	US-202016910662-A
Country	US
Kind code	A1
Filing date	Jun 24, 2020
Priority date	Mar 28, 2014
Publication date	Oct 15, 2020
Grant date	—

Abstract

An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.

First claim

What is claimed is:

1 . A device comprising:
a semiconductor substrate formed of a first semiconductor material; a plurality of semiconductor fins extending from the semiconductor substrate; an insulating layer surrounding the semiconductor fins, the insulating layer having a topmost surface a first height above the semiconductor substrate and an intermediate surface a second lesser height above the semiconductor substrate; a gate stack extending over the plurality of semiconductor fins, the gate stack extending down respective sidewalls of respective ones of the plurality of semiconductor fins and having a bottom surface in contact with the topmost surface of the insulating layer; each semiconductor fin of the plurality of semiconductor fins including a source/drain region on a side of the gate stack, wherein the source/drain region comprises:
a first portion having a substantially columnar shape, when viewed in cross section, the first portion extending to a height above the intermediate surface of the insulating layer, and
a second portion having a substantially faceted shape, when viewed in cross section, the second portion extending to a height from the topmost surface of the insulating layer to above the topmost surface of the insulating; and
a source/drain contact electrically connecting respective source/drain regions of respective semiconductor fins of the plurality of semiconductor fins, the source/drain contact extending below the topmost surface of the insulating layer and contacting the intermediate surface of the insulating layer.

2 . The device of claim 1 , wherein a bottommost surface of at least one source/drain region is below a bottommost surface of the insulating layer.

3 . The device of claim 1 , further comprising respective interfaces between respective fins and respective source/drain regions and wherein the respective interfaces are below a second interface between the insulating layer and the semiconductor substrate.

4 . The device of claim 1 , wherein respective first portions have opposite sidewalls that are substantially parallel to each other.

5 . The device of claim 1 , further comprising a source/drain silicide region extending between and electrically connecting at least two source/drain regions.

6 . The device of claim 1 , further comprising a silicide layer extending between two fins, the silicide layer including a horizontal portion atop the semiconductor substrate.

7 . The device of claim 1 , wherein respective contact plugs extend below an interface between respective first portions and respective second portions of respective source/drain regions.

8 . The device of claim 1 , wherein respective second portions have a substantially diamond-shaped profile.

9 . The device of claim 1 , wherein respective second portions have rounded corners.

10 . A device comprising:
a semiconductor substrate formed of a first semiconductor material and having a semiconductor fin extending from a major surface thereof; an insulation region extending into the semiconductor substrate and at least partially surrounding the semiconductor fin; a gate stack extending over a top and sidewalls of the semiconductor fin; a source/drain region adjacent a side of the gate stack, the source/drain region including
a first portion; and
a second portion that extends from the first portion and extends above a topmost surface of the insulating region, the second portion having faceted sidewalls that extend out laterally from the first portion, wherein the first portion and the second portion comprise a semiconductor material that is different than the semiconductor fin material.

11 . The device of claim 10 , wherein the first portion is substantially columnar in shape.

12 . The device of claim 10 , wherein the second portion is substantially diamond-shaped in profile with rounded corners.

13 . The device of claim 10 , further comprising a silicide of the source/drain region.

14 . The device of claim 13 , wherein the silicide comprises a portion extending between the source/drain region and a second source/drain region.

15 . The device of claim 10 , wherein the insulation region has a topmost surface a first height above the semiconductor substrate and an intermediate surface a second lesser height above the semiconductor substrate.

16 . The device of claim 15 , further comprising a contact plug electrically connected to the source/drain region.

17 . The device of claim 16 , further comprising an Inter-Layer Dielectric (ILD) over the source/drain region, wherein the contact plug extends from a top surface of the ILD to the intermediate surface of the insulation region.

18 . A method comprising:
forming an insulator layer surrounding a semiconductor fin; forming a gate stack over the semiconductor fin, the gate stack extending to a topmost surface of the insulator layer; etching a portion of the semiconductor fin to leave a recess in the insulator layer, wherein a semiconductor material is exposed at a bottom of the recess; epitaxially growing a source/drain region to fill the recess and to extend above the recess with faceted surfaces; depositing a second insulator layer above the source/drain region and above the insulator layer; forming a contact opening through the second insulator layer and partially through the insulator layer, the contact opening exposing the source/drain region, the contact opening further having a bottom defined by an intermediate surface of the insulator layer, the intermediate surface being below the topmost surface of the insulator layer; and forming a contact in the contact opening, the contact having a bottommost surface that contacts the intermediate surface of the insulator layer.

19 . The method of claim 18 :
wherein the step of forming an insulator layer surrounding a semiconductor fin includes performing a first recessing of the insulator layer to form isolation regions, wherein a semiconductor region between the isolation regions forms the semiconductor fin and the semiconductor fin protrudes higher than a first top surface s of the insulator layer; and and further comprising performing a second recessing to recess the isolation regions, so that sidewalls of the sidewalls of the source/drain region in contact with the recessed isolation regions are exposed.

20 . The method of claim 19 , wherein after the second recessing, a bottom portion of the source/drain region has a sidewall contacting a remaining portion of the isolation regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Yu-Lien
• Lee Tung Ying

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10D64/0112

  using conductive layers comprising silicides · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title

• H10W20/033

  in openings in dielectrics · CPC title