Noise reduction in sense amplifiers for non-volatile memory

Patent metadata

Field	Value
Publication number	US-12361984-B2
Application number	US-202318346359-A
Country	US
Kind code	B2
Filing date	Jul 3, 2023
Priority date	Mar 30, 2023
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Techniques are presented to reduce sense amplifier noise from parasitic capacitances that can affect the internal transfer of a data value from a data latch to a sensing node. To transfer the data value, the sensing node is pre-charged and the data value used to set the control gate voltage on a transistor in a discharge path for the sensing node. In the discharge path, the transistor is connected in series with a switch, so that when the switch is turned on, the data value on the transistor's control gate will determine whether or not the sensing node discharges. To reduce noise in the process, before the data value is used to bias the discharge path transistor's control gate, a node between the transistor and switch is charged. Additionally, a lower voltage level can be used to turn on the discharge path switch.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality of bit lines each connected to one or more non-volatile memory cells, the control circuit comprising:
a sensing circuit comprising:
a first sensing node configured to connect to one or more of the bit lines;
a local data bus;
one or more internal data latches connected to the local data bus; and
a first discharge path connected between the first sensing node and a first discharge node and comprising:
an intermediate node;
a first discharge switch connected between the first sensing node and the intermediate node; and
a first sensing node discharge transistor connected between the intermediate node and the first discharge node and having a control gate connected to the local data bus,

where, to transfer a first data value from a first of the internal data latches to the first sensing node, the control circuit is configured to:
pre-charge the first sensing node;
bias the first discharge node to a high voltage level for the sensing circuit;
pre-charge the local data bus to thereby charge the intermediate node from the first discharge node through the first sensing node discharge transistor while the first discharge node is biased to the high voltage level for the sensing circuit;
subsequent to charging the intermediate node, bias the first discharge node to a low voltage level;
subsequent to charging the intermediate node, set a voltage level on local data bus according to the first data value; and
subsequent to pre-charging the first sensing node, biasing the first discharge node to a low voltage level and charging the intermediate node, turn on the first discharge switch for a first discharge interval.

2. The non-volatile memory device of claim 1 , wherein the control circuit is formed on a control die, the non-volatile memory device further comprising:
a memory die including the non-volatile memory cells, the memory die separate from and bonded to the control die.

3. The non-volatile memory device of claim 1 , wherein the sensing circuit comprises a plurality of switches in addition to the first discharge switch, and the control circuit is further configured to turn on the plurality of switches other than the first discharge switch using a first high logic level, and further configured to turn on the first discharge switch for a for first discharge interval using a second high logic level, the second high logic level being lower than the first high logic level.

4. The non-volatile memory device of claim 3 , wherein to bias the first discharge node to the high voltage level for the sensing circuit, the first discharge node is biased to the second high logic level.

5. The non-volatile memory device of claim 1 , the sensing circuit further comprising:
a second discharge path connected between the local data bus and a second discharge node and comprising:
a second discharge switch; and
a first sensing node discharge transistor connected in series with the second discharge switch between the local data bus and the second discharge node and having a control gate connected to the first sensing node,

wherein, subsequent to transferring the first data value from the first of the internal data latches to the first sensing node, to transfer the first data value from the first sensing node to the local data bus, the control circuit is further configured to:
pre-charge the local data; and
subsequent to pre-charging the local data bus, turn on the second discharge switch for a second discharge interval.

6. The non-volatile memory device of claim 5 , wherein, subsequent to transferring the first data value from the first sensing node to the local data bus, the control circuit is further configured to latch the transferred first data value on the local data bus in one of the internal data latches.

7. The non-volatile memory device of claim 5 , the sensing circuit further comprising:
an external data bus connectable to the local data bus,

wherein, subsequent to transferring the first data value from the first sensing node to the local data bus, the control circuit is further configured to further transfer the first data value from the local data bus to the external data bus.

8. The non-volatile memory device of claim 7 , the sensing circuit further comprising:
a transfer data latch connected to the external data bus,

wherein, subsequent to further transferring the first data value from the local data bus to the external data bus, the control circuit is further configured to latch the transferred first data value on the external data bus in the transfer data latch.

9. The non-volatile memory device of claim 5 , wherein the second discharge node is the same as the first discharge node.

10. The non-volatile memory device of claim 1 , wherein in transferring the first data value from a first of the internal data latches to the first sensing node, an inverse of the first data value is transferred to the first sensing node.

11. The non-volatile memory device of claim 1 , wherein, subsequent to transferring the first data value from the first of the internal data latches to the first sensing node, the control circuit is further configured to latch a new data value in the first internal data latch.

12. The non-volatile memory device of claim 1 , further comprising the bit lines and the non-volatile memory cells, wherein the control circuit further configured to:
pre-charge the first sensing node for a first sensing operation of a selected memory cell along a first bit line;
discharge the pre-charged first sense node through the selected memory cell by an amount dependent on a programmed state of the selected memory cell; and
based on the amount the first sense node discharged, latch a sensed data value in the internal data latches.

13. The non-volatile memory device of claim 1 , wherein the sensing circuit further comprises a second sensing node and to pre-charge the first sensing node, the control circuit is further configured to:
pre-charge the second sensing node; and
pre-charge the first sensing node from the second sensing node.

14. A method, comprising:
pre-charging a sensing node of a sense amplifier circuit;
charging an intermediate node of a first discharge path for the sense amplifier circuit connected between the sensing node and a first discharge node, the first discharge path including the intermediate node, a first discharge switch connected between the sensing node and the intermediate node, and a first sensing node discharge transistor connected between the intermediate node and the first discharge node and having a control gate connected to a local data bus, charging of the intermediate node comprising:
biasing the first discharge node to a high voltage level for sense amplifier circuit; and
pre-charging the local data bus, where the local data bus is pre-charged concurrently with the first discharge node biased to the high voltage level for the sense amplifier circuit;

subsequent to charging the intermediate node, biasing the first discharge node to a low voltage level;
subsequent to charging the intermediate node, setting a voltage level on local data bus according to a first data value from an internal data latch connected to the local data bus; and
subsequent to pre-charging the sensing node, biasing the first discharge node to a low voltage level and charging the intermediate node, turning on the first discharge switch for a first discharge interval to transfer the first data value from the internal data latch to the sensing node.

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Lu Iris
• Wu Yonggang
• Tei Kou
• Kwon Ohwon

Classifications

• G11C7/1039 Primary

  using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers · CPC title

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title