Semiconductor memory device including memory cells at opposing sides of semiconductor

Patent metadata

Field	Value
Publication number	US-11264106-B2
Application number	US-202017016580-A
Country	US
Kind code	B2
Filing date	Sep 10, 2020
Priority date	Nov 26, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A semiconductor memory device includes separate first and second word lines respectively facing first and second portions of a semiconductor and sandwiching the semiconductor; and first and second cell transistors respectively located in the first and second portions and respectively coupled to the first and second word lines. In a first operation, a first read is executed on the second cell transistor while a first voltage and a higher second voltage are being respectively applied to the first and second word lines. In a second operation, a second read is executed on the first cell transistor while a third voltage between the first and second voltages is being applied to the second word line.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a semiconductor including a first portion and a second-portion;
a first word line facing the first portion of the semiconductor;
a second word line facing the second portion of the semiconductor, sandwiching the semiconductor with the first word line, and being separate from the first word line;
a first cell transistor located in the first portion of the semiconductor and coupled to the first word line; and
a second cell transistor located in the second portion of the semiconductor and coupled to the second word line,
wherein
in a first operation, a first read is executed in which data based on a threshold voltage of the second cell transistor is acquired while a first voltage is being applied to the first word, line and a second voltage higher than the first voltage is being applied to the second word line, and
in a second operation, a second read is executed in which data based on a threshold voltage of the first cell transistor is acquired while a third voltage higher than the first voltage and lower than the second voltage is being applied to the second word line.

2. The device of claim 1 , wherein
in the first operation, a third read is executed in which data based on the threshold voltage of the second cell transistor is acquired while the first voltage is being applied to the first word line and a fourth voltage higher than the first voltage and different from the second voltage is being applied to the second word line, and
in the second operation, a fourth read is executed in which data based on the threshold voltage of the first cell transistor is acquired while a fifth voltage higher than the first voltage and lower than the fourth voltage is being applied to the second word line.

3. The device of claim 2 , wherein
the second voltage is lower than the fourth voltage and the fifth voltage,
in the first operation, a fifth read is executed in which data, based on the threshold voltage of the second cell transistor is acquired while the first voltage is being applied to the first word line and a sixth voltage higher than the fourth voltage is being applied to the second word line, and
in the second operation, a sixth read is executed in which data based on the threshold voltage of the first cell transistor is acquired while a seventh voltage higher than the fourth voltage and lower than the sixth voltage is being applied to the second word line.

4. The device of claim 3 , wherein
one of the second voltage, the fourth voltage and the sixth voltage is applied to the first word line in the second read, the fourth read, and the sixth read.

5. The device of claim 3 , wherein
in the second operation, the fourth read is executed after the sixth read, and the second read is executed after the fourth read.

6. The device of claim 3 , wherein
in the first operation, the third read is executed after the first read, and the fifth read is executed after the third read.

7. The device of claim 3 , wherein
in the first operation, the third read is executed after the fifth read, and the first read is executed after the third read.

8. The device of claim 3 , wherein
the seventh voltage is applied to the first word line during the second read,
an eighth voltage different from the seventh voltage is applied to the first word line during the fourth read, and
a ninth voltage different, from the seventh voltage and the eighth voltage is applied to the first word line during the sixth read.

9. The device of claim 3 , wherein
in the second operation, a seventh read is executed in which data based on the threshold voltage of the first cell transistor is acquired, while an eighth voltage lower than the first voltage is being applied to the second word line.

10. The device of claim 9 , wherein
the first voltage is a negative voltage.

11. The device of claim 1 , wherein
the second operation is executed subsequently to the first operation.

12. The device of claim 1 , wherein
the first operation is executed subsequently to the second operation.

13. The device of claim 1 , wherein
the semiconductor further includes a third portion,
the device further comprises:
a third word line facing the third portion of the semiconductor, sandwiching the semiconductor with the first word line, and being separate from the first word line and the second word line; and
a third cell transistor located in the third portion of the semiconductor and coupled to the third word line,

in the second operation, data based on the threshold voltage of the first cell transistor is acquired while the third voltage is being applied to the first word line and the third word line.

14. A semiconductor memory device comprising:
a semiconductor including a first portion and a second portion;
a first word line facing the first portion of the semiconductor;
a second word line facing the second portion of the semiconductor, sandwiching the semiconductor with the first word line, and being separate from the first word line;
a first cell transistor located in the first portion of the semiconductor and coupled to the first word line;
a second cell transistor located in the second portion of the semiconductor and coupled to the second word line;
a bit line electrically coupled to the first cell transistor and the second cell transistor; and
a sense amplifier including a first node electrically coupled to the bit line, and acquiring data based on a potential on the first node when receiving a first signal of a first logical level,
wherein
in a first operation, the sense amplifier receives the first signal of the first logical level while a first voltage is being applied to the first word line and a second voltage higher than the first voltage is being applied to the second word line, and
in a second operation, the sense amplifier receives the first signal of the first logical level while a third voltage higher than the first voltage and lower than the second voltage is being applied to the second word line.

15. The device of claim 14 , wherein
in the first operation, the sense amplifier receives the first signal of the first logical level while the first voltage is being applied to the first word line and a fourth voltage higher than the first voltage and different from the second voltage is being applied to the second word line, and
in the second operation, the sense amplifier receives the first signal of the first logical level while a fifth voltage higher than the first voltage and lower than the fourth voltage is being applied to the second word line.

16. The device of claim 15 , wherein
the second voltage is lower than the fourth voltage and the fifth voltage,
in the first operation, the sense amplifier receives the first signal of the first logical level while the first voltage is being applied to the first word line and a sixth voltage higher than the fourth voltage is being applied to the second word line, and
in the second operation, the sense amplifier receives the first signal of the first logical level while a seventh voltage higher than the fourth voltage and lower than the sixth voltage is being applied to the second word line.

17. The device of claim 16 , wherein
the application of the third voltage, the application of the fifth voltage, and the application of the seventh voltage are executed while one of the second voltage, the fourth voltage and the sixth voltage is being applied to the first word line.

18. The device of claim 16 , wherein
the application of the fifth

Assignees

• Kioxia Corp

Inventors

• Maejima Hiroshi
• Shiga Hidehiro
• Kondo Masaki

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/32

  Timing circuits · CPC title