Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-10210924-B2
Application number	US-201715690256-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Jan 23, 2017
Publication date	Feb 19, 2019
Grant date	Feb 19, 2019

Abstract

A semiconductor memory device includes a memory cell transistor, a bit line, a sense amplifier circuit, a voltage generation circuit, and a control unit. The bit line is electrically connected to a terminal of the memory cell transistor. The sense amplifier circuit includes a first transistor having a gate electrically connected to the bit line and a second transistor connected in series to a first terminal of the first transistor. The control unit controls the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first sense period and a second voltage to the second terminal of the first transistor during a second sense period. The first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first and second voltages have voltage levels different from each other.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell transistor;
a bit line that is electrically connected to a terminal of the memory cell transistor;
a sense amplifier circuit that includes a first transistor having a gate which is connected to the bit line through a plurality of transistors, which when turned on, electrically connects the gate of the first transistor to the bit line, and a second transistor having a first terminal which is connected in series to a first terminal of the first transistor;
a voltage generation circuit having an output electrically connected to a second terminal of the first transistor;
and a control unit configured to control the voltage generation circuit to apply a first voltage to the second terminal of the first transistor during a first period in a program verification operation and a second voltage to the second terminal of the first transistor during a second period in the program verification operation following the first period, wherein
the first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V and the first voltage and the second voltage have voltage levels different from each other.

2. The semiconductor memory device according to claim 1 , wherein the second period directly follows the first period, and the first voltage is higher than 0 V and lower than the second voltage.

3. The semiconductor memory device according to claim 1 , wherein the control unit is configured to execute a program operation on the memory cell transistor followed by a verification operation on the memory cell transistor, and the first and second periods occur during the verification operation.

4. The semiconductor memory device according to claim 3 , wherein the control unit, during the program operation on the memory cell transistor, sets the bit line to one of at least three voltage levels depending on whether a verification operation on the memory cell transistor following a prior program operation on the memory cell transistor failed completely, failed partially, or passed.

5. The semiconductor memory device according to claim 1 , further comprising:
a latch circuit configured to latch a voltage level at a sense node that is electrically connected to the gate of the first transistor, wherein
the control unit, during each of the first and second periods, turns the second transistor on and off, to transfer the voltage level at the sense node to the latch circuit.

6. The semiconductor memory device according to claim 5 , wherein
the latch circuit has first and second sets of transistors electrically connected in series between a high voltage node and a low voltage node, and
the control unit controls the voltage generation circuit during the first and second periods to apply the same voltage applied to the second terminal of the first transistor, to the low voltage node.

7. The semiconductor memory device according to claim 5 , wherein
the latch circuit has first and second sets of transistors electrically connected in series between a high voltage node and a low voltage node which is electrically connected to ground.

8. The semiconductor memory device according to claim 7 , wherein
a data bus connecting the sense amplifier circuit to the latch circuit is grounded through a third transistor, and
the control unit, during each of the first and second periods, turns the third transistor on and off after turning the second transistor on and off.

9. A method of performing a write operation in a semiconductor memory device including a memory cell transistor, a bit line that is electrically connected to a terminal of the memory cell transistor, a sense amplifier circuit that includes a first transistor having a gate which is connected to the bit line through a plurality of transistors, which when turned on, electrically connects the gate of the first transistor to the bit line, and a second transistor having a first terminal which is connected in series to a first terminal of the first transistor, and a voltage generation circuit having an output electrically connected to a second terminal of the first transistor, said method comprising:
performing a program operation on the memory cell transistor; and then
performing a verification operation on the memory cell transistor,
wherein during the verification operation, a first voltage is applied to the second terminal of the first transistor during a first period in a program verification operation and a second voltage is applied to the second terminal of the first transistor during a second period in the program verification operation following the first period, and
the first voltage is equal to or higher than 0 V and the second voltage is higher than 0 V, and the first voltage and the second voltage have voltage levels different from each other.

10. The method according to claim 9 , wherein the second period directly follows the first period, and the first voltage is higher than 0 V and lower than the second voltage.

11. The method according to claim 9 , further comprising:
performing a subsequent program operation on the memory cell transistor, wherein
during the subsequent program operation, the bit line is set to one of at least three voltage levels depending on whether the verification operation on the memory cell transistor failed completely, failed partially, or passed.

12. The method according to claim 9 , wherein
the semiconductor memory device further includes a latch circuit configured to latch a voltage level at a sense node that is electrically connected to the gate of the first transistor, and
during each of the first and second periods, the second transistor is turned on and off to transfer the voltage level at the sense node to the latch circuit.

13. The method according to claim 12 , wherein
the latch circuit has first and second sets of transistors electrically connected in series between a high voltage node and a low voltage node, and
during the first and second periods, the same voltage applied to the second terminal of the first transistor is applied to the low voltage node.

14. The method according to claim 12 , wherein
the latch circuit has first and second sets of transistors electrically connected in series between a high voltage node and a low voltage node which is electrically connected to ground.

15. The method according to claim 14 , wherein
the semiconductor memory device further includes a data bus that connects the sense amplifier circuit to the latch circuit and is connected to ground through a third transistor, and
during each of the first and second periods, the third transistor is turned on and off after the second transistor is turned on and off.

16. A semiconductor memory device comprising:
a memory cell transistor;
a bit line that is electrically connected to a terminal of the memory cell transistor;
a sense amplifier circuit that includes a first transistor having a gate which is connected to the bit line through a plurality of transistors, which when turned on, electrically connects the gate of the first transistor to the bit line, and a second transistor having a first terminal which is connected in series to a first terminal of the first transistor;
a voltage generation circuit having an output electrically connected to a second terminal of the second transistor;
and a control unit configured to control the voltage generation circuit to apply a first voltage to the second terminal of the second transistor during a first period in a program verification operation, a second voltage to the second termi

Assignees

• Toshiba Memory Corp

Inventors

• Kamata Yoshihiko

Classifications

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title