Volatile memory with a decreased consumption and an improved storage capacity

Patent metadata

Field	Value
Publication number	US-9007848-B2
Application number	US-201313754427-A
Country	US
Kind code	B2
Filing date	Jan 30, 2013
Priority date	Feb 3, 2012
Publication date	Apr 14, 2015
Grant date	Apr 14, 2015

Abstract

A volatile memory includes volatile memory cells in which data write and read operations are performed. The memory cells are arranged in rows and in columns and are distributed in first separate groups of memory cells for each column. The memory includes, for each column, a write bit line dedicated to write operations and connected to all the memory cells of the column and read bit lines dedicated to read operations. Each read bit line is connected to all the memory cells of one of the first groups of memory cells. Each memory cell in the column is connected to a single one of the read bit lines.

First claim

What is claimed is:

1. A volatile memory comprising:
a plurality of volatile memory cells arranged in rows and in columns and being distributed in first separate groups of memory cells for each column;
a plurality of write bit lines, each write bit line dedicated to write operations and coupled to all the memory cells in an associated column;
a plurality of read bit lines dedicated to read operations, each read bit line being coupled to all the memory cells of only one of the first groups of memory cells, each memory cell in a particular column being coupled to a single one of the read bit lines;
for each column, a multiplexer coupled to all the read bit lines and configured to receive a control signal; and
for each column, an amplifier, the multiplexer configured to deliver the signal present on one of the read bit lines to the amplifier according to the control signal.

2. The memory of claim 1 , wherein the memory cells are distributed in second separate groups of memory cells for each row, the memory comprising a first memory cell selection circuit dedicated to write operations and a second memory cell selection circuit, different from the first circuit, dedicated to read operations, wherein the first circuit is capable of selecting, for each row, memory cells from one of the first groups of memory cells for a write operation and the second circuit is capable of selecting, for each row, memory cells from one of the first groups of memory cells for a read operation.

3. The volatile memory of claim 2 , wherein the second selection circuit comprises read word lines for each row, each read word line being coupled to all the memory cells of one of the second groups of memory cells, for each row, each memory cell in the row being coupled to a single one of the read word lines.

4. The volatile memory of claim 3 , wherein each memory cell comprises:
first and second inverters, an output of the first inverter being coupled to an input of the second inverter and an output of the second inverter being coupled to an input of the first inverter;
a first switch coupled to the output of the first inverter;
a second switch coupled to the output of the second inverter;
a first MOS transistor having two first conduction terminals and a first gate, the first gate being coupled to the output of the first inverter; and
a second MOS transistor having two second conduction terminals and a second gate, the second gate being coupled to the output of the second inverter;
wherein each read word line is coupled to one of the first conduction terminals and to one of the second conduction terminals; and
wherein the first selection circuit comprises a circuit capable of turning on the first and second switches of one of the groups of memory cells.

5. The volatile memory of claim 4 , further comprising, for each column and for each first group of the column, first and second read bit lines, wherein the other one of the first conduction terminals of the first MOS transistor is coupled to the first read bit line and the other one of the second conduction terminals of the second MOS transistor is coupled to the second read bit line.

6. The volatile memory of claim 4 , wherein the first switch comprises a third MOS transistor coupled between the output of the first inverter to a first write bit line and wherein the second switch comprises a fourth MOS transistor coupled between the output of the second inverter to a second write bit line.

7. The volatile memory of claim 6 , wherein the first selection circuit comprises write word lines for each row, each write word line being coupled to the gates of the third and fourth MOS transistors of the memory cells of one of the groups of memory cells.

8. The volatile memory of claim 6 , wherein the first selection circuit comprises a third inverter, the output of the third inverter being coupled to the gates of the third and fourth transistors and the input of the third inverter being coupled to a write word line.

9. The volatile memory of claim 6 , wherein the first selection circuit comprises a fifth MOS transistor interposed between the third MOS transistor and the first write bit line (BLT) and a sixth MOS transistor interposed between the fourth MOS transistor and the second write bit line.

10. An electronic device comprising:
a battery; and
a memory array that is powered by the battery, the memory array comprising:
a plurality of volatile memory cells to which data write and read operations are performed, the memory cells being arranged in rows and in columns and being distributed in first separate groups of memory cells for each column;
a plurality of write bit lines, each write bit line dedicated to write operations and coupled to all the memory cells in an associated column;
a plurality of read bit lines dedicated to read operations, each read bit line being coupled to all the memory cells of only one of the first groups of memory cells, each memory cell in a particular column being coupled to a single one of the read bit lines;
for each column, a multiplexer coupled to all the read bit lines and configured to receive a control signal; and
for each column, an amplifier, the multiplexer configured to deliver the signal present on one of the read bit lines to the amplifier according to the control signal.

11. The memory of claim 10 , wherein the memory cells are distributed in second separate groups of memory cells for each row, the memory comprising a first memory cell selection circuit dedicated to write operations and a second memory cell selection circuit, different from the first circuit, dedicated to read operations, wherein the first circuit is capable of selecting, for each row, memory cells from one of the first groups of memory cells for a write operation and the second circuit is capable of selecting, for each row, memory cells from one of the first groups of memory cells for a read operation.

12. The volatile memory of claim 11 , wherein the second selection circuit comprises read word lines for each row, each read word line being coupled to all the memory cells of one of the second groups of memory cells, for each row, each memory cell in the row being coupled to a single one of the read word lines.

13. The volatile memory of claim 12 , wherein each memory cell comprises:
first and second inverters, an output of the first inverter being coupled to an input of the second inverter and an output of the second inverter being coupled to an input of the first inverter;
a first switch coupled to the output of the first inverter;
a second switch coupled to the output of the second inverter;
a first MOS transistor having two first conduction terminals and a first gate, the first gate being coupled to the output of the first inverter; and
a second MOS transistor having two second conduction terminals and a second gate, the second gate being coupled to the output of the second inverter;
wherein each read word line is coupled to one of the first conduction terminals and to one of the second conduction terminals; and
wherein the first selection circuit comprises a circuit capable of turning on the first and second switches of one of the groups of memory cells.

14. The volatile memory of claim 13 , further comprising, for each column and for each first group of the column, first and second read bit lines, wherein the other one of the first conduction terminals of the first MOS transistor is coupled to the first read bit line and the other one of the second conduction terminals of the second MOS transistor is coupled to the second read bit line.

15. The volatile memory of claim

Assignees

• St Microelectronics Sa

Inventors

• Feki Anis

Classifications

• G11C7/18 Primary

  Bit line organisation; Bit line lay-out · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C8/16

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title