Dynamic clock tree planning using feedtiming cost

Patent metadata

Field	Value
Publication number	US-12361194-B2
Application number	US-202217831367-A
Country	US
Kind code	B2
Filing date	Jun 2, 2022
Priority date	Jun 11, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.

First claim

What is claimed is:

1. A method comprising:
identifying, by a processing device, a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution;
identifying, by the processing device, one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution;
receiving a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies; and
generating the circuit design according to the selection.

2. The method of claim 1 , wherein the first clock tree topology and the one or more additional clock tree topologies each comprise a respective clock path extending from a clock source to a load.

3. The method of claim 2 , wherein the circuit design comprises one or more circuit components arranged in a physical layout, and wherein the threshold feedthrough count and the different respective feedthrough counts each comprise a respective number of times that the respective clock path crosses a boundary of the one or more circuit components.

4. The method of claim 3 , wherein generating the circuit design according to the selection comprises forming the clock path with respect to the one or more circuit components to have the respective feedthrough count of the selected clock tree topology.

5. The method of claim 1 , wherein identifying the one or more additional clock tree topologies comprises:
performing a number of iterations of a clock tree topology process incorporating a feed-timing cost parameter, each iteration to identify a respective additional clock tree topology;
setting an allowed feedthrough count to zero for a first iteration of the number of iterations; and
incrementing the allowed feedthrough count by a set amount for any additional iterations of the number of iterations.

6. The method of claim 5 , wherein the feed-timing cost parameter comprises a vector of path-length and encountered feedthroughs count.

7. The method of claim 1 , further comprising:
causing presentation of the first clock tree topology and the one or more additional clock tree topologies for selection in a user interface.

8. A system comprising:
a memory; and
a processing device, coupled to the memory and configured to perform operations comprising:
identifying a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution;
identifying one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution;
receiving a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies; and
generating the circuit design according to the selection.

9. The system of claim 8 , wherein the first clock tree topology and the one or more additional clock tree topologies each comprise a respective clock path extending from a clock source to a load.

10. The system of claim 9 , wherein the circuit design comprises one or more circuit components arranged in a physical layout, and wherein the threshold feedthrough count and the different respective feedthrough counts each comprise a respective number of times that the respective clock path crosses a boundary of the one or more circuit components.

11. The system of claim 10 , wherein generating the circuit design according to the selection comprises forming the clock path with respect to the one or more circuit components to have the respective feedthrough count of the selected clock tree topology.

12. The system of claim 8 , wherein identifying the one or more additional clock tree topologies comprises:
performing a number of iterations of a clock tree topology process incorporating a feed-timing cost parameter, each iteration to identify a respective additional clock tree topology;
setting an allowed feedthrough count to zero for a first iteration of the number of iterations; and
incrementing the allowed feedthrough count by a set amount for any additional iterations of the number of iterations.

13. The system of claim 12 , wherein the feed-timing cost parameter comprises a vector of path-length and encountered feedthroughs count.

14. The system of claim 8 , wherein the processing device is configured to perform operations further comprising:
causing presentation of the first clock tree topology and the one or more additional clock tree topologies for selection in a user interface.

15. A non-transitory computer-readable storage medium storing instructions which, when executed, cause a processing device to perform operations comprising:
identifying, by the processing device, a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution;
identifying, by the processing device, one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution;
receiving a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies; and
generating the circuit design according to the selection.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the first clock tree topology and the one or more additional clock tree topologies each comprise a respective clock path extending from a clock source to a load.

17. The non-transitory computer-readable storage medium of claim 16 , wherein the circuit design comprises one or more circuit components arranged in a physical layout, and wherein the threshold feedthrough count and the different respective feedthrough counts each comprise a respective number of times that the respective clock path crosses a boundary of the one or more circuit components.

18. The non-transitory computer-readable storage medium of claim 15 , wherein identifying the one or more additional clock tree topologies comprises:
performing a number of iterations of a clock tree topology process incorporating a feed-timing cost parameter, each iteration to identify a respective additional clock tree topology;
setting an allowed feedthrough count to zero for a first iteration of the number of iterations; and
incrementing the allowed feedthrough count by a set amount for any additional iterations of the number of iterations.

19. The non-transitory computer-readable storage medium of claim 18 , wherein the feed-timing cost parameter comprises a vector of path-length and encountered feedthroughs count.

20. The non-transitory computer-readable storage medium of claim 15 , wherein the instructions cause the processing device to perform operations further comprising:
causing presentation of the first clock tree topology and the one or more additional clock tree topologies for selection in a user interface.

Assignees

• Synopsys Inc

Inventors

• Kumar Vivek
• Gupta Prashant

Classifications

• G06F30/398

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/373

  Design optimisation · CPC title

• G06F30/337

  Design optimisation · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title