Graphical analysis of complex clock trees

Patent metadata

Field	Value
Publication number	US-10255396-B2
Application number	US-201715482306-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Apr 7, 2016
Publication date	Apr 9, 2019
Grant date	Apr 9, 2019

Abstract

This application discloses a computing system to implement a place and route tool to synthesize a clock tree in a layout design of an integrated circuit based on timing constraints for the integrated circuit. The computing system can select a portion of the clock tree to present in a schematic connectivity presentation based on a conformance of the portion of the clock tree to timing constraints for the clock tree. The computing system can compress the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree. The compacted representation can retain a hierarchical connectivity of the other portions of the clock tree. The computing system can generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree coupled to at least one compacted representation of other portions of the clock tree.

First claim

The invention claimed is:

1. A method comprising:
synthesizing, by a computing system, a clock tree in a layout design of an integrated circuit based, at least in part, on timing constraints for the integrated circuit;
selecting, by the computing system, a portion of the clock tree to present in a schematic connectivity presentation;
generating, by the computing system, the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree, which is coupled to at least one compacted representation of other portions of the clock tree in the schematic connectivity presentation of the clock tree;
extracting, by the computing system, one or more clock tree circuits from the compacted representation based, at least in part, on a retained hierarchical connectivity of the other portions of the clock tree in the compacted representation; and
modifying, by the computing system, the schematic connectivity presentation of the clock tree to include the extracted clock tree circuits coupled to a modified-version of the compacted representation that excludes the extracted clock tree circuits.

2. The method of claim 1 , further comprising prompting, by the computing system, presentation of the schematic connectivity presentation of the clock tree on a display device.

3. The method of claim 1 , further comprising compressing, by the computing system, the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree to present in the schematic connectivity presentation.

4. The method of claim 3 , wherein compressing the other portions of the clock tree into the compacted representation retains the hierarchical connectivity of the other portions of the clock tree.

5. The method of claim 1 , wherein extracting the clock tree circuits from the compacted representation further comprises removing false re-convergence of the extracted clock tree circuits in the clock tree.

6. The method of claim 1 , wherein selecting the portion of the clock tree to present in the schematic connectivity presentation is based, at least in part, on a conformance of the portion of the clock tree to the timing constraints for the clock tree.

7. A system comprising:
a memory device configured to store machine-readable instructions; and
a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
synthesize a clock tree in a layout design of an integrated circuit based, at least in part, on timing constraints for the integrated circuit;
select a portion of the clock tree to present in a schematic connectivity presentation;
generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree, which is coupled to at least one compacted representation of other portions of the clock tree in the schematic connectivity presentation of the clock tree;
extract one or more clock tree circuits from the compacted representation based, at least in part, on a retained hierarchical connectivity of the other portions of the clock tree in the compacted representation; and
modify the schematic connectivity presentation of the clock tree to include the extracted clock tree circuits coupled to a modified-version of the compacted representation that excludes the extracted clock tree circuits.

8. The system of claim 7 , wherein the one or more processing devices, in response to executing the machine-readable instructions, are configured to compress the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree to present in the schematic connectivity presentation.

9. The system of claim 8 , wherein the compression of the other portions of the clock tree into the compacted representation retains the hierarchical connectivity of the other portions of the clock tree.

10. The system of claim 7 , wherein the extraction of the clock tree circuits from the compacted representation removes false re-convergence of the extracted clock tree circuits in the clock tree.

11. The system of claim 7 , wherein the selection of the portion of the clock tree to present in the schematic connectivity presentation is based, at least in part, on a conformance of the portion of the clock tree to the timing constraints for the clock tree.

12. An apparatus including a memory device storing instructions configured to cause one or more processing devices to perform operations comprising:
synthesizing a clock tree in a layout design of an integrated circuit based, at least in part, on timing constraints for the integrated circuit;
selecting a portion of the clock tree to present in a schematic connectivity presentation;
generating the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree, which is coupled to at least one compacted representation of other portions of the clock tree in the schematic connectivity presentation of the clock tree;
extracting one or more clock tree circuits from the compacted representation based, at least in part, on a retained hierarchical connectivity of the other portions of the clock tree in the compacted representation; and
modifying the schematic connectivity presentation of the clock tree to include the extracted clock tree circuits coupled to a modified-version of the compacted representation that excludes the extracted clock tree circuits.

13. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising prompting presentation of the schematic connectivity presentation of the clock tree on a display device.

14. The apparatus of claim 12 , wherein the instructions are configured to cause one or more processing devices to perform operations further comprising compressing the other portions of the clock tree into the compacted representation based on the selection of the portion of the clock tree to present in the schematic connectivity presentation.

15. The apparatus of claim 14 , wherein compressing the other portions of the clock tree into the compacted representation retains the hierarchical connectivity of the other portions of the clock tree.

16. The apparatus of claim 12 , wherein extracting the clock tree circuits from the compacted representation further comprises removing false re-convergence of the extracted clock tree circuits in the clock tree.

17. The apparatus of claim 12 , wherein selecting the portion of the clock tree to present in the schematic connectivity presentation is based, at least in part, on a conformance of the portion of the clock tree to the timing constraints for the clock tree.

Assignees

• Mentor Graphics Corp

Inventors

• Bouzouzou Hamid
• Ribet Pierre-Olivier
• Blanks Daniel
• Richier Patrick
• Masse-Navette Laurent

Classifications

• G06F30/327

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/396 Primary

  Clock trees · CPC title

• G06F17/505

  Physics · mapped topic

• G06F2217/62

  Physics · mapped topic