Method for forming semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-12356637-B2
Application number	US-202117411108-A
Country	US
Kind code	B2
Filing date	Aug 25, 2021
Priority date	Aug 13, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A method for forming semiconductor structure includes: providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, lower portions of the supporting structures including a bottom conducting layers, and capacitor openings being included between the supporting structures, and the bottom conducting layers being electrically connected with the conducting layers; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the bottom conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer), to form a capacitor structure. A semiconductor structure is also provided.

First claim

The invention claimed is:

1. A method for forming semiconductor structure, comprising the following steps:
providing a semiconductor substrate, which at least comprises discrete conducting layers in the semiconductor substrate;
forming discretely arranged supporting structures on the semiconductor substrate, lower portions of the supporting structures comprising bottom conducting layers, wherein a width of each one of the bottom conducting layers is less than or equal to ⅓ of a width of each one of the multiple supporting structures in a direction parallel to a top surface of the semiconductor substrate, capacitor openings being comprised between the supporting structures, and the bottom conducting layers being electrically connected with the conducting layers;
forming lower electrodes only on sidewalls of the supporting structures, the lower electrodes being electrically connected with the bottom conducting layers;
forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and
forming an upper electrode covering the capacitor dielectric layer, to form a capacitor structure.

2. The method for forming semiconductor structure of claim 1 , wherein the step of forming the discretely arranged supporting structures on the semiconductor substrate comprises:
forming the bottom conducting layers on the semiconductor substrate;
forming a supporting layer on the bottom conducting layers; and
patterning the supporting layer and the bottom conducting layers to form the capacitor opening, and form the supporting structures by the remaining supporting layer and bottom conducting layers.

3. The method for forming semiconductor structure of claim 2 , wherein the step of forming the bottom conducting layers on the semiconductor substrate and forming the supporting layers on the bottom conducting layers comprises:
forming a bottom conducting film on the semiconductor substrate;
patterning the bottom conducting film to form through holes that penetrate through the bottom conducting film, and taking the remaining bottom conducting film as the bottom conducting layer; and
forming the supporting layer on the bottom conducting layer, and the supporting layer also filling the through holes.

4. The method for forming semiconductor structure of claim 2 , wherein patterning the supporting layer to form multiple discrete capacitor openings comprises:
sequentially forming a mask layer and a patterned photoresist layer on the supporting layer;
patterning the mask layer based on the photoresist layer; and
etching the supporting layer and the bottom conducting layer based on the patterned mask layer to form the capacitor openings.

5. The method for forming semiconductor structure of claim 2 , wherein a capacitor opening at least exposes part of a top surface of each of the discrete conducting layers.

6. The method for forming semiconductor structure of claim 2 , wherein the supporting layer is consisted of a bottom supporting layer and a filling layer that are sequentially stacked.

7. The method for forming semiconductor structure of claim 1 , wherein the step of forming the discretely arranged supporting structures on the semiconductor substrate comprises:
forming discretely arranged initial supporting structures on the semiconductor substrate, wherein each one of the initial supporting structures comprises a bottom supporting layer and a filling layer that are sequential stacked;
laterally etching the bottom supporting layer of a partial width to form a conducting opening; and
forming the bottom conducting layer filling the conducting opening, the supporting structures being formed, by the bottom conducting layer and remaining initial supporting structures.

8. The method for forming semiconductor structure of claim 7 , wherein a width of the conducting opening is less than or equal to ⅓ of a width of the bottom supporting layer in a direction parallel to a top surface of the semiconductor substrate.

9. The method for forming semiconductor structure of claim 7 , wherein the step of forming the bottom conducting layer filling the conducting opening comprises:
forming a bottom conducting film filling the conducting opening and a part of height of the capacitor opening, and a level of a top surface of the bottom conducting film is higher than a level of a top surface of the bottom supporting layer; and
etching away the bottom conducting film exposed from the capacitor opening to form the bottom conducting layer.

10. The method for forming semiconductor structure of claim 1 , wherein the step of forming the lower electrodes electrically connected with the conducting layers on the sidewalls of the supporting structures comprises:
forming a top conducting layer at the tops and sidewalls of the supporting structures and the bottoms of the capacitor openings; and
removing the top conducting layer on the tops of the supporting structures and the bottoms of the capacitor openings to form the lower electrodes on the sidewalls of the supporting structures.

11. The method for forming semiconductor structure of claim 10 , wherein a means for removing the top conducting layer on the tops of the supporting structures comprises chemical mechanical polishing.

12. The method for forming semiconductor structure of claim 1 , wherein the step of forming the upper electrode covering the capacitor dielectric layer comprises:
forming a first conducting layer covering the capacitor dielectric layer; and
forming a second conducting layer filling a gap between the first conducting layer, a top surface of the second conducting layer being parallel to a top surface of the first conducting layer on the supporting structures, and a level of the top surface of the second conducting layer is higher than a level of the top surface of the first conducting layer on the supporting structures.

13. The method for forming semiconductor structure of claim 12 , wherein the step of forming the second conducting layer filling the gap between the first conducting layer comprises:
forming a second conducting film filling the gap between the first conducting layer, and the level of the top surface of the second conducting film is higher than the level of the top surface of the first conducting layer on the supporting structures; and
performing a chemical mechanical polishing treatment on the top surface of the second conducting film to form the second conducting layer.

14. A semiconductor structure, comprising:
a semiconductor substrate, wherein the semiconductor substrate at least comprises discrete conducting layers;
multiple discrete supporting structures located on the semiconductor substrate, wherein a lower portion of each one of the multiple discrete supporting structures at least comprises a bottom conducting layer, and the bottom conducting layer is electrically connected with each one of the discrete conducting layers; wherein a width of the bottom conducting layer is less than or equal to ⅓ of a width of each one of the multiple discrete supporting structures in a direction parallel to a top surface of the semiconductor substrate; and
capacitor structures supported by each one of the multiple discrete supporting structures, wherein each one of the capacitor structures comprises:
a lower electrode, located only on a sidewall of each one of the multiple discrete supporting structures and electrically connected with the bottom conducting layer;
a capacitor dielectric layer, located on a top of each one of the multiple discrete supporting structures, a sidewall of the lower elec

Assignees

• Changxin Memory Tech Inc

Inventors

• Wang Lingxiang

Classifications

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title

• H10B12/033

  the capacitor extending over the transistor · CPC title