Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9859296-B2
Application number	US-201615160335-A
Country	US
Kind code	B2
Filing date	May 20, 2016
Priority date	Sep 9, 2015
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on the substrate;
a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate;
a semiconductor pattern between the channel pattern and the substrate;
a conductive pattern between the channel pattern and the semiconductor pattern, the conductive pattern electrically connecting the channel pattern to the semiconductor pattern,
the conductive pattern contacting a bottom edge of the channel pattern and an upper surface of the semiconductor pattern; and
an insulation structure including a plurality of stacked patterns, the insulation structure disposing between the channel pattern and the semiconductor pattern, wherein the insulation structure contacts an inner sidewall of the conductive pattern.

2. The semiconductor device of claim 1 , wherein the conductive pattern includes polysilicon.

3. The semiconductor device of claim 1 , wherein the conductive pattern directly contacts the bottom edge of the channel pattern.

4. The semiconductor device of claim 1 , wherein the conductive pattern contacts the bottom edge and a lower sidewall of the channel pattern.

5. The semiconductor device of claim 1 , further comprising:
a data storage structure between the channel pattern and the gates, wherein the data storage structure includes a tunnel insulation pattern, a charge storage pattern and a blocking pattern.

6. The semiconductor device of claim 5 , wherein the conductive pattern contacts the bottom edge of the channel pattern, a lower sidewall of the channel pattern, and a bottom of the data storage structure.

7. The semiconductor device of claim 1 , wherein the insulation structure directly contact a top surface of the semiconductor pattern, and
at least one of the stacked patterns protrudes from a different one of the stacked patterns in a lateral direction.

8. The semiconductor device of claim 7 , wherein a width of each of the stacked patterns of the insulation structure is smaller than a width of a bottom of the channel pattern.

9. The semiconductor device of claim 1 , further comprising:
a lower gate surrounding a sidewall of the semiconductor pattern, wherein
the lower gate extends in a direction parallel to the top surface of the substrate.

10. The semiconductor device of claim 1 , wherein at least one of
an entire portion of the insulation structure is between a bottom surface of the channel pattern and the upper surface of the semiconductor pattern in the first direction, and
an entire portion of the conductive pattern is between the bottom edge of the channel pattern and the upper surface of the semiconductor pattern in the first direction.

11. A semiconductor device, comprising: a substrate; a plurality of gates on the substrate, the gates being spaced apart from each other and the substrate in a first direction substantially perpendicular to a top surface of the substrate; a channel structure extending through the gates in the first direction, the channel structure being spaced apart from the top surface of the substrate, and the channel structure including a channel pattern and a data storage structure extending along a sidewall of the channel pattern; a conductive pattern between the channel pattern and the substrate, the conductive pattern electrically connecting the channel pattern to the substrate, the conductive pattern contacting a bottom edge of the channel pattern and the top surface of the substrate, the conductive pattern includes a middle portion between a bottom portion and a top portion in the first direction, and the middle portion and the bottom portion have different widths in a second direction parallel to the top surface of the substrate; and an insulation structure between the channel pattern and the substrate, wherein the insulation structure contacts an inner sidewall of the conductive pattern, the insulation structure includes stacked patterns, and at least one of the stacked patterns protrudes from a different one of the stacked patterns in the second direction.

12. The semiconductor device of claim 11 , wherein a bottom of the data storage structure is above a bottom of the channel pattern.

13. The semiconductor device of claim 11 , further comprising:
a semiconductor pattern between the substrate and the conductive pattern; and
a lower gate surrounding a sidewall of the semiconductor pattern, wherein
the lower gate extends in a direction parallel to the top surface of the substrate.

14. A semiconductor device, comprising: a substrate; a channel pattern on the substrate, the channel pattern extending in a first direction that is vertical to a top surface of the substrate; a conductive pattern between the substrate and an edge part of a bottom surface of the channel pattern, the conductive pattern being electrically connected to the channel pattern through the edge part of the bottom surface of the channel pattern; an insulation structure between the substrate and the center part of the bottom surface of the channel pattern, the center part of the bottom surface of the channel pattern being on top of a top surface of the insulation structure, the conductive pattern surrounding the insulating structure; a data storage structure surrounding the channel pattern; a plurality of gates surrounding the data storage structure, the plurality of gates being spaced apart from each other in the first direction above the substrate; and a semiconductor pattern on the substrate, wherein the conductive pattern is on top of the semiconductor pattern, and the conductive pattern electrically connects the channel pattern to the semiconductor pattern, an entire portion of the insulation structure is between the center part of the bottom surface of the channel pattern and an upper surface of the semiconductor pattern in the first direction, and an entire portion of the conductive pattern is between the bottom edge of the channel pattern and an upper surface of the semiconductor pattern in the first direction.

15. The semiconductor device of claim 14 , wherein
the insulating structure includes a first pattern, a second pattern, and a third pattern sequentially stacked on top of each other and surrounded by the conductive pattern,
a width of the second pattern is different than a width of the first and third patterns.

16. The semiconductor device of claim 15 , wherein
the data storage structure includes a tunnel insulating pattern, a charge storage pattern, and a blocking pattern, and
the first to third patterns includes the same materials as the blocking pattern, the charge storage pattern, and the tunnel insulating pattern, respectively.

Assignees

• Park Se-Jun
• Yun Jang-Gn
• Hwang Sung-Min
• Moon Ahn-Sik
• Xia Zhiliang
• Samsung Electronics Co Ltd

Inventors

• Park Se-Jun
• Yun Jang-Gn
• Hwang Sung-Min
• Moon Ahn-Sik
• Xia Zhiliang

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/1157 Primary

  Electricity · mapped topic

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title