Emission height arrangements in light-emitting diode packages and related devices and methods

US12355013B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12355013-B2
Application numberUS-202217726072-A
CountryUS
Kind codeB2
Filing dateApr 21, 2022
Priority dateApr 21, 2022
Publication dateJul 8, 2025
Grant dateJul 8, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Light-emitting diode (LED) packages and more particularly emission height arrangements in LED packages and related devices and methods are disclosed. LED packages, LED chips, and related device arrangements are disclosed that include various combinations of LED chip types, lumiphoric materials, and/or cover structures that are arranged together while also providing a substantially uniform emission height for corresponding light-emitting surfaces. LED chips may be configured with different heights or thicknesses that compensate for variations in lumiphoric materials and/or cover structures utilized to provide different emission colors. Corresponding LED packages and/or LED chips with different emission colors may be assembled near one another with improved emission height uniformity.

First claim

Opening claim text (preview).

What is claimed is: 1. A method comprising: providing a first light-emitting diode (LED) chip and a first lumiphoric material layer that define a first color point; providing a second LED chip that defines a second color point that is different than the first color point; and reducing a thickness of at least one of the first LED chip and the second LED chip such that a first emission height formed by the first LED chip and the first lumiphoric material layer is within 100 microns (μm) of a second emission height of the second LED chip. 2. The method of claim 1 , wherein the first emission height is defined as a perpendicular distance from a mounting surface of the first LED chip to a topmost emission surface of the first LED chip, and the second emission height is defined as a perpendicular distance from a mounting surface of the second LED chip to a topmost emission surface of the second LED chip. 3. The method of claim 2 , wherein the topmost emission surface of the first LED chip is defined at a topmost surface of the first lumiphoric material layer and the topmost emission surface of the second LED chip is defined at a topmost surface of the second LED chip. 4. The method of claim 1 , wherein the thickness of the first LED chip is reduced by an amount that corresponds with a thickness of the first lumiphoric material layer. 5. The method of claim 1 , wherein reducing a thickness of at least one of the first LED chip and the second LED chip comprises reducing a thickness of a substrate of at least one of the first LED chip and the second LED chip. 6. The method of claim 1 , wherein the first emission height is within 60 μm of the second emission height. 7. The method of claim 1 , wherein the first emission height is within 30 μm of the second emission height. 8. The method of claim 1 , wherein the first LED chip is on a first submount, and the second LED chip is on a second submount that has a same height as the first submount. 9. A method comprising: providing a first light-emitting diode (LED) chip and a first lumiphoric material layer that define a first color point; providing a second LED chip and a second lumiphoric material layer that define a second color point that is different than the first color point; and reducing a thickness of at least one of the first LED chip and the second LED chip such that a first emission height formed by the first LED chip and the first lumiphoric material layer is within 100 microns (μm) of a second emission height formed by the second LED chip and the second lumiphoric material layer. 10. The method of claim 9 , wherein the first emission height is defined as a perpendicular distance from a mounting surface of the first LED chip to a topmost emission surface of the first LED chip, and the second emission height is defined as a perpendicular distance from a mounting surface of the second LED chip to a topmost emission surface of the second LED chip. 11. The method of claim 10 , wherein the topmost emission surface of the first LED chip is defined at a topmost surface of the first lumiphoric material layer and the topmost emission surface of the second LED chip is defined at a topmost surface of the second lumiphoric material layer. 12. The method of claim 9 , wherein reducing a thickness of at least one of the first LED chip and the second LED chip comprises reducing a thickness of a substrate of at least one of the first LED chip and the second LED chip. 13. The method of claim 9 , wherein the first emission height is within 60 μm of the second emission height. 14. The method of claim 9 , wherein the first emission height is within 30 μm of the second emission height. 15. The method of claim 9 , wherein the first LED chip and the second LED chip are on a same mounting surface of a submount.

Assignees

Inventors

Classifications

  • H10W90/00Primary

    Package configurations · CPC title

  • of coatings · CPC title

  • Coatings, e.g. passivation layers or antireflective coatings · CPC title

  • Manufacture or treatment · CPC title

  • of wavelength conversion means · CPC title

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What does patent US12355013B2 cover?
Light-emitting diode (LED) packages and more particularly emission height arrangements in LED packages and related devices and methods are disclosed. LED packages, LED chips, and related device arrangements are disclosed that include various combinations of LED chip types, lumiphoric materials, and/or cover structures that are arranged together while also providing a substantially uniform emiss…
Who is the assignee on this patent?
Creeled Inc
What technology area does this patent fall under?
Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).