Three-dimensional memory device and fabrication method

Patent metadata

Field	Value
Publication number	US-12354994-B2
Application number	US-202217838910-A
Country	US
Kind code	B2
Filing date	Jun 13, 2022
Priority date	Jun 13, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a conductor/insulator stack over a substrate, forming a dielectric layer of a dielectric material including atomic hydrogen over a part of the conductor/insulator stack, and performing a thermal process to release the atomic hydrogen from the dielectric material and diffuse the atomic hydrogen into the conductor/insulator stack.

First claim

What is claimed is:

1. A method for fabricating a three-dimensional (3D) memory device, comprising:
forming a conductor/insulator stack over a substrate;
forming a dielectric layer of a dielectric material including atomic hydrogen over the conductor/insulator stack;
forming a plurality of semiconductor channels through the conductor/insulator stack; and
performing a thermal process to release the atomic hydrogen from the dielectric material and diffuse the atomic hydrogen into the conductor/insulator stack, wherein the plurality of semiconductor channels contains atomic hydrogen.

2. The method according to claim 1 , wherein the dielectric material includes hydrogenated silicon nitride.

3. The method according to claim 1 , wherein the atomic hydrogen is released from a plurality of hydrogen bonds of the dielectric material.

4. The method according to claim 3 , wherein the plurality of hydrogen bonds include a silicon-hydrogen (Si—H) bond and/or a nitrogen-hydrogen (N—H) bond.

5. The method according to claim 1 , further comprising:
diffusing the atomic hydrogen into the conductor/insulator stack to passivate a plurality of defects in the conductor/insulator stack by binding the atomic hydrogen with the plurality of defects, respectively.

6. The method according to claim 1 , further comprising:
forming a plurality of vias that extend through the dielectric layer for interconnect.

7. The method according to claim 6 , further comprising:
forming a plurality of conductor layers over the plurality of vias for interconnect.

8. The method according to claim 6 , wherein the thermal process is performed before forming the plurality of vias.

9. The method according to claim 6 , wherein the thermal process is performed before bonding an 3D array device with a peripheral device to form the 3D memory device, the 3D array device and peripheral device including the conductor/insulator stack and a complementary metal-oxide semiconductor (CMOS) circuit, respectively.

10. A three-dimensional (3D) memory device, comprising:
a conductor/insulator stack;
a dielectric layer of a dielectric material including atomic hydrogen disposed over the conductor/insulator stack;
a plurality of semiconductor channels through the conductor/insulator stack and containing atomic hydrogen; and
a plurality of vias through the dielectric layer.

11. The 3D memory device according to claim 10 , wherein the dielectric material includes hydrogenated silicon nitride.

12. The 3D memory device according to claim 10 , wherein the dielectric material includes a plurality of hydrogen bonds that release atomic hydrogen in a thermal process.

13. The 3D memory device according to claim 12 , wherein the plurality of hydrogen bonds include a silicon-hydrogen (Si—H) bond and/or a nitrogen-hydrogen (N—H) bond.

14. The 3D memory device according to claim 10 , further comprising:
functional layers formed through the conductor/insulator stack and between the conductor/insulator stack and a semiconductor channel of the plurality of semiconductor channels, wherein the functional layers further contain atomic hydrogen.

15. The 3D memory device according to claim 12 , further comprising:
a periphery device bonded with a 3D array device that includes the conductor/insulator stack, the periphery device including a complementary metal-oxide semiconductor (CMOS) circuit that facilitates an operation of the 3D memory device.

16. The 3D memory device according to claim 14 , wherein the functional layers include a blocking layer adjacent to the conductor/insulator stack, a charge trap layer on the blocking layer, and a tunneling layer on the charge trap layer.

17. A memory apparatus, comprising:
an input/output (I/O) component for receiving an input;
a buffer for buffering a signal;
a controller for implementing an operation; and
a three-dimensional (3D) memory device, the 3D memory device comprising:
a conductor/insulator stack;
a dielectric layer of a dielectric material including atomic hydrogen disposed over the conductor/insulator stack;
a plurality of semiconductor channels through the conductor/insulator stack and containing atomic hydrogen; and
a plurality of vias through the dielectric layer.

18. The memory apparatus according to claim 17 , wherein the dielectric material includes hydrogenated silicon nitride.

19. The memory apparatus according to claim 17 , wherein the dielectric material includes a plurality of hydrogen bonds that release atomic hydrogen in a thermal process.

20. The memory apparatus according to claim 17 , wherein the 3D memory device further includes:
a plurality of conductor layers proximate to the dielectric layer, the dielectric layer being between the plurality of conductor layers and the conductor/insulator stack.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Lu Zhiyong
• Peng Sheng
• Yu Kai
• Zhang Wenbo
• Zhou Yang
• Gao Jing

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/041

  Thermally treating · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title