Chip package structure and storage system

Patent metadata

Field	Value
Publication number	US-12354941-B2
Application number	US-202217844200-A
Country	US
Kind code	B2
Filing date	Jun 20, 2022
Priority date	Jan 13, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A chip package structure and a storage system are provided. The chip package structure includes a chipset, a first Re-Distribution Layer (RDL), and a bonding pad region. The chipset includes a plurality of chips distributed horizontally. The first RDL is disposed on a first surface of the chipset. The bonding pad region includes a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL.

First claim

The invention claimed is:

1. A chip package structure, comprising:
a chipset, wherein the chipset comprises a plurality of chips distributed horizontally;
a first Re-Distribution Layer (RDL) disposed on a first surface of the chipset; and
a bonding pad region, wherein the bonding pad region comprises a plurality of bonding pads, the plurality of bonding pads are located on a side surface of the first RDL away from the chipset, and the plurality of bonding pads are connected to the plurality of chips through the first RDL; wherein all bonding pads corresponding to the plurality of chips are centrally disposed in the bonding pad region;
wherein a horizontal area of the bonding pad region is less than or equal to a total horizontal area of the first surface of the chipset;
the horizontal area of the bonding pad region is less than or equal to a horizontal area of any one of the plurality of chips, and
an orthographic projection of the bonding pad region on the first surface is within an orthographic projection of one of the plurality of chips on the first surface.

2. The chip package structure of claim 1 , wherein the plurality of bonding pads comprise a first bonding pad and a second bonding pad,
the first bonding pad is simultaneously connected to at least two of the plurality of chips through the first RDL, and
the second bonding pad is connected to one of the plurality of chips through the first RDL.

3. The chip package structure of claim 1 , wherein
the orthographic projection of the bonding pad region on the first surface is located in a center of the first surface.

4. The chip package structure of claim 1 , wherein
each of the plurality of chips comprises multilayer sub-chips stacked onto one another vertically, and the multilayer sub-chips are interconnected with each other by a set of Through Silicon Vias (TSV).

5. The chip package structure of claim 4 , wherein each of the multilayer sub-chips comprises a memory chip, a control chip or a processor chip.

6. The chip package structure of claim 1 , wherein the first RDL comprises a plurality of communication buses, a plurality of power buses and a ground bus,
wherein each communication bus corresponds to and is connected to one of the plurality of chips, and the plurality of bonding pads respectively transmit communication signals for the plurality of chips through the plurality of communication buses corresponding to the plurality of chips,
each power bus corresponds to and is connected to the plurality of chips, and one of the plurality of bonding pads transmits a power signal for the plurality of chips through one of the plurality of power buses corresponding to the plurality of chips, and
one of the plurality of bonding pads connects the plurality of chips to a ground terminal through the ground bus.

7. The chip package structure of claim 6 , wherein the plurality of communication buses comprise a shared line and a layered line,
the shared line is configured to transmit a communication signal shared by the multilayer sub-chips, and
the layered line is configured to transmit a communication signal used by each layer of sub-chip of the multilayer sub-chips individually.

8. The chip package structure of claim 7 , wherein
the plurality of communication buses are configured to transmit at least one of a command signal, an address signal, a layer selection signal, or a data signal.

9. The chip package structure of claim 8 , wherein
the layered line is configured to transmit the data signal,
the shared line is configured to transmit the command signal, the address signal and the layer selection signal.

10. A storage system, comprising: a first storage module, wherein the first storage module comprises the chip package structure according to claim 1 .

11. The storage system of claim 10 , further comprising a processing module,
wherein the processing module comprises a plurality of processor groups distributed horizontally, and the processing module is in bonding connection with the first storage module.

12. The storage system of claim 11 , wherein
a second Re-Distribution Layer (RDL) is disposed on a second surface of the processor groups, wherein the second surface face the first surface.

13. The storage system of claim 12 , wherein
each of the first RDL and the second RDL is obtained by connecting a metal interconnection line with a metal plug,
each of the first RDL and the second RDL is filled with a dielectric layer.

14. The storage system of claim 12 , wherein a third bonding pad is disposed on a side of the second RDL away from the second surface,
the third bonding pad is bonded to the first bonding pad and the second bonding pad by a solder ball.

15. The storage system of claim 11 , further comprising a second storage module, wherein the second storage module is in bonding connection with a side surface of the first storage module away from the processing module.

Assignees

• Changxin Memory Tech Inc

Inventors

• Ning Shu-Liang
• He Jun
• Liu Jie
• Ying Zhan

Classifications

• H10W90/792

  between multiple chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W80/743

  having disposition changed during the connecting · CPC title

• H10W80/721

  having structure or size changed during the connecting · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title