Memory packages and related semiconductor packages

Patent metadata

Field	Value
Publication number	US-10586775-B2
Application number	US-201816174934-A
Country	US
Kind code	B2
Filing date	Oct 30, 2018
Priority date	Jan 22, 2018
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

First claim

What is claimed is:

1. A memory package comprising:
a multi-level package substrate including a plurality of wiring layers and a plurality of insulating layers that are alternately stacked;
a first memory chip on the multi-level package substrate, the first memory chip including a plurality of first memory cells and a first receiver;
a second memory chip on the first memory chip, the second memory chip including a plurality of second memory cells and a second receiver;
a first band pass filter in the multi-level package substrate, the first band pass filter connected to the first receiver and configured to pass a first data signal within a first frequency band; and
a second band pass filter in the multi-level package substrate, the second band pass filter connected to the second receiver and configured to pass a second data signal within the first frequency band.

2. The memory package of claim 1 :
wherein the multi-level package substrate includes a first wiring layer, a second wiring layer and a first insulating layer between the first wiring layer and the second wiring layer; and
wherein the first band pass filter includes at least one passive element that is formed substantially vertically with respect to a first surface of the multi-level package substrate such that the at least one passive element is included in both the first wiring layer and the second wiring layer.

3. The memory package of claim 2 , wherein the first band pass filter comprises:
a first capacitor including a first electrode in the first wiring layer and a second electrode in the second wiring layer; and
a first inductor penetrating the first insulating layer.

4. The memory package of claim 3 , wherein the first capacitor and the first inductor are connected in parallel with each other.

5. The memory package of claim 4 , wherein the first band pass filter further comprises:
a first line in the first wiring layer, the first line configured to connect the first electrode of the first capacitor with a first end of the first inductor; and
a second line in the second wiring layer, the second line configured to connect the second electrode of the first capacitor with a second end of the first inductor.

6. The memory package of claim 5 , further comprising:
a first conductive bump configured to receive the first data signal from an external device;
a first connection line configured to connect the first conductive bump with the first line; and
a first bonding wire configured to connect the first line with the first memory chip.

7. The memory package of claim 6 , wherein the first conductive bump, the first connection line and the first bonding wire are formed on a first path for transmitting the first data signal to the first receiver.

8. The memory package of claim 6 , further comprising:
a second conductive bump configured to receive a ground voltage from the external device; and
a second connection line configured to connect the second conductive bump with the second line.

9. The memory package of claim 3 , wherein the first capacitor includes a multi-layer ceramic capacitor (MLCC).

10. The memory package of claim 1 :
wherein the multi-level package substrate includes a first wiring layer, a second wiring layer and a first insulating layer between the first wiring layer and the second wiring layer; and
wherein the first band pass filter includes at least one passive element that is included in one of the first wiring layer and the second wiring layer.

11. The memory package of claim 10 , wherein the first band pass filter comprises:
a first capacitor in the first wiring layer; and
a first inductor in the first wiring layer, the first capacitor and the first inductor being connected in parallel with each other.

12. The memory package of claim 1 , wherein the first band pass filter is connected to a first node on a first path for transmitting the first data signal to the first receiver.

13. The memory package of claim 12 , wherein a direct current (DC) path is not formed by the first band pass filter.

14. The memory package of claim 1 , wherein each of the first memory chip and the second memory chip includes a dynamic random access memory (DRAM) device.

15. The memory package of claim 14 , wherein the first memory chip and the second memory chip have a same structure.

16. A semiconductor package comprising:
a multi-level package substrate including a plurality of wiring layers and a plurality of insulating layers that are alternately stacked;
a controller chip on the multi-level package substrate, the controller chip configured to receive a first data signal and a second data signal;
a first memory chip on the multi-level package substrate and spaced apart from the controller chip, the first memory chip including a plurality of first memory cells and a first receiver;
a second memory chip on the first memory chip, the second memory chip including a plurality of second memory cells and a second receiver;
a first band pass filter in the multi-level package substrate, the first band pass filter connected to the first receiver and configured to pass the first data signal within a first frequency band, the first data signal being output from the controller chip; and
a second band pass filter in the multi-level package substrate, the second band pass filter connected to the second receiver and configured to pass a second data signal within the first frequency band, the second data signal being output from the controller chip.

17. The semiconductor package of claim 16 , further comprising:
a first signal path configured to connect the controller chip with the first memory chip, and to transmit the first data signal from the controller chip to the first receiver; and
a second signal path configured to connect the controller chip with the second memory chip, and to transmit the second data signal from the controller chip to the second receiver.

18. The semiconductor package of claim 17 , wherein at least a part of the first signal path and the second signal path is formed in the multi-level package substrate.

19. A semiconductor package comprising:
a lower package substrate;
a controller chip on the lower package substrate, the controller chip configured to receive a first data signal and a second data signal;
a multi-level upper package substrate on the lower package substrate on which the controller chip is formed, the multi-level upper package substrate including a plurality of wiring layers and a plurality of insulating layers that are alternately stacked;
a first memory chip on the multi-level upper package substrate, the first memory chip including a plurality of first memory cells and a first receiver;
a second memory chip on the first memory chip, the second memory chip including a plurality of second memory cells and a second receiver;
a first band pass filter in the multi-level upper package substrate, the first band pass filter connected to the first receiver and configured to pass the first data signal within a first frequency band, the first data signal being output from the controller chip; and
a second band pass filter in the multi-level upper package substrate, the second band pass filter connected to the second receiver and configured to pass a second data signal within the first frequency band, the second data signal being output from the controller chip.

20. The semiconductor package of claim 19 , further comprising a via between a lower package and an upper package, the lower package inc

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong-Uk
• Kim Il-Joon

Classifications

• H03H7/0115

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H03H2001/0085

  Multilayer, e.g. LTCC, HTCC, green sheets · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title