Semiconductor device

Patent metadata

Field	Value
Publication number	US-9917026-B2
Application number	US-201415515465-A
Country	US
Kind code	B2
Filing date	Dec 24, 2014
Priority date	Dec 24, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a wiring substrate;
an interposer mounted on a first surface of the wiring substrate;
a first semiconductor component mounted on the interposer;
a second semiconductor component mounted on the interposer, and controlling the first semiconductor component, the first semiconductor component and the second semiconductor component being arranged next to each other; and
a plurality of external terminals formed on a second surface of the wiring substrate, which is opposite to the first surface,
wherein the interposer includes a base member made of a semiconductor material as a base material and a plurality of wiring layers arranged on a main surface of the base member,
wherein the first semiconductor component and the second semiconductor component are electrically connected to each other via the plurality of wiring layers,
wherein the plurality of wiring layers include a first wiring layer, a second wiring layer spaced farther away from the main surface of the base member than the first wiring layer, and a third wiring layer spaced farther away from the main surface of the base member than the second wiring layer,
wherein, in a first region of the interposer which is sandwiched between the first semiconductor component and the second semiconductor component and also in plan view, a ratio of reference potential wirings, which constitute a part of a transmission path of a reference potential, in the third wiring layer is higher than a ratio of the reference potential wirings in the first wiring layer, and
wherein, in the first region of the interposer and also in plan view, a ratio of signal wirings, which constitute a part of a signal transmission path, in the first wiring layer is higher than a ratio of the signal wirings in the third wiring layer.

2. The semiconductor device according to claim 1 ,
wherein the base member contains an impurity element constituting a conductive characteristic of a first conductivity type or a second conductivity type opposite to the first conductivity type.

3. The semiconductor device according to claim 2 ,
wherein the signal wirings include first signal wirings through which a first signal is transmitted at a first frequency band and second signal wirings through which a second signal is transmitted at a second frequency band higher than the first frequency band,
wherein, in the first region of the interposer which is sandwiched between the first semiconductor component and the second semiconductor component and also in plan view, a ratio of the first signal wirings the signal wirings arranged in the first wiring layer is higher than a ratio of the second signal wirings, and
wherein, in the first region of the interposer and also in plan view, a ratio of the first signal wirings the signal wirings arranged in the second wiring layer is lower than a ratio of the second signal wirings.

4. The semiconductor device according to claim 3 ,
wherein the second signal wirings are not formed in the first wiring layer.

5. The semiconductor device according to claim 3 ,
wherein a separation distance between the third wiring layer and the second wiring layer is larger than a separation distance between the first wiring layer and the second wiring layer.

6. The semiconductor device according to claim 5 ,
wherein the plurality of wiring layers of the interposer further include an uppermost wiring layer which is spaced farther away from the main surface of the base member than the third wiring layer and in which a plurality of first electrode pads are formed, and
wherein a separation distance between the uppermost wiring layer and the third wiring layer is larger than the separation distance between the third wiring layer and the second wiring layer.

7. The semiconductor device according to claim 2 ,
wherein a plurality of first electrode pads are formed in the third wiring layer of the interposer, and
wherein the plurality of first electrode pads are electrically connected to the first semiconductor component or the second semiconductor component via a plurality of bump electrodes.

8. The semiconductor device according to claim 7 ,
wherein first electrode pads for a reference potential, which constitute a part of the transmission path of the reference potential, in the plurality of first electrode pads formed in the third wiring layer of the interposer are connected to be formed in a sheet shape.

9. The semiconductor device according to claim 1 ,
wherein a separation distance between the plurality of wiring layers of the interposer and a separation distance between the first wiring layer and the main surface of the base member are smaller than each thickness of the plurality of wiring layers.

10. The semiconductor device according to claim 1 ,
wherein a separation distance between the third wiring layer and the second wiring layer is larger than a separation distance between the second wiring layer and the first wiring layer.

11. The semiconductor device according to claim 3 ,
wherein the first semiconductor component includes a first circuit,
wherein the second semiconductor component includes a second circuit that controls an operation of the first circuit of the first semiconductor component, and
wherein the first semiconductor component and the second semiconductor component are electrically connected to each other via the first signal wirings, the second signal wirings, and the reference potential wirings.

12. The semiconductor device according to claim 11 ,
wherein the first signal wirings and the second signal wirings are electrically isolated from the wiring substrate, and the reference potential wirings are electrically connected to the wiring substrate.

13. The semiconductor device according to claim 2 ,
wherein the plurality of wiring layers of the interposer further include an uppermost wiring layer which is spaced farther away from the main surface of the base member than the third wiring layer and in which a plurality of first electrode pads are formed, and
wherein the reference potential wirings formed in the third wiring layer have a mesh shape in plan view.

14. The semiconductor device according to claim 2 ,
wherein the plurality of wiring layers of the interposer further include an uppermost wiring layer which is spaced farther away from the main surface of the base member than the third wiring layer and in which a plurality of first electrode pads are formed, and
wherein a separation distance between the uppermost wiring layer and the third wiring layer is larger than a separation distance between the third wiring layer and the second wiring layer.

15. The semiconductor device according to claim 1 ,
wherein the plurality of wiring layers of the interposer further include an uppermost wiring layer which is spaced farther away from the main surface of the base member than the third wiring layer and in which a plurality of first electrode pads are formed, and
wherein a wiring is not formed in the uppermost wiring layer in the first region.

16. A semiconductor device comprising:
a wiring substrate;
an interposer mounted on a first surface of the wiring substrate;
a first semiconductor component mounted on the interposer;
a second semiconductor component mounted on the interposer, and controlling the first semiconductor component, the first semiconductor component and the second semiconductor component being arranged next to each other; and
a plurality of external terminals formed on a second surface of the wiring substrate, which is opposite to the

Assignees

• Renesas Electronics Corp

Inventors

• Oikawa Ryuichi
• Ochiai Toshihiko
• Kariyazaki Shuuichi
• Kayashima Yuji
• Kida Tsuyoshi

Classifications

• H10W90/752

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/223

  Differential pair signal lines · CPC title