Semiconductor device

Patent metadata

Field	Value
Publication number	US-12354927-B2
Application number	US-202217700498-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Sep 9, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A semiconductor device including a package, a lid and a thermal interface material is provided. The package includes a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies. The lid is disposed on the packaging substrate, the lid includes a cover portion and foot portion extending from the cover portion to the packaging substrate, wherein the cover portion covers the semiconductor dies and the insulating encapsulation, the foot portion includes foot segments laterally spaced apart from one another, and the foot segments are attached to the packaging substrate. The cover portion of the lid is attached to the package through the thermal interface material.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a package comprising a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies;
a lid disposed on the packaging substrate, the lid comprising a rectangular cover portion and foot portion extending from the rectangular cover portion to the packaging substrate, wherein the rectangular cover portion covers the semiconductor dies and the insulating encapsulation, the foot portion comprises foot segments laterally spaced apart from one another, and the foot segments are attached to the packaging substrate, and wherein the foot segments comprise first foot segments arranged along a pair of short sides of the rectangular cover portion and second foot segments arranged along a pair of long sides of the rectangular cover portion, the first foot segments provide a first stiffness, and the second foot segments provide a second stiffness greater than the first stiffness; and
a thermal interface material, wherein the rectangular cover portion of the lid is attached to the package through the thermal interface material.

2. The semiconductor device of claim 1 , wherein the package further comprises an interposer disposed between the packaging substrate and the semiconductor dies encapsulated by the insulating encapsulation, and the semiconductor dies are electrically connected to the packaging substrate through the interposer.

3. The semiconductor device of claim 1 , wherein the package comprises an integrated fanout structure assembled on packaging substrate.

4. The semiconductor device of claim 1 , wherein the foot portion of the lid comprises grooves, and the foot segments are laterally spaced apart from one another by the grooves.

5. The semiconductor device of claim 1 , wherein the first foot segments are spaced apart from one another by first grooves, and the second foot segments are spaced apart from one another by second grooves.

6. The semiconductor device of claim 5 , wherein a first extending direction of the first grooves is substantially paralleled with the pair of long sides of the rectangular cover portion, a second extending direction of the second grooves is substantially paralleled with the pair of short sides of the rectangular cover portion, and a first maximum width of the first grooves is greater than a second maximum width of the second grooves.

7. The semiconductor device of claim 5 , wherein a first depth of the first grooves is substantially equal to or greater than a second depth of the second grooves.

8. The semiconductor device of claim 1 , wherein the rectangular cover portion further comprises a ring-shaped indentation defining an attachment portion of the rectangular cover portion, and the attachment portion is in contact with the thermal interface material.

9. The semiconductor device of claim 1 , wherein the rectangular cover portion further comprises a protruding attachment portion, and the protruding attachment portion protrudes toward the package and is in contact with the thermal interface material.

10. A semiconductor device, comprising:
a package comprising a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies;
a lid disposed on the packaging substrate, the lid comprising a rectangular cover portion, a foot portion and stiffness adjustment grooves, wherein the foot portion extends from the cover portion to the package, and the stiffness adjustment grooves laterally extend across the foot portion, and wherein a first area occupied by first foot segments among the foot segments arranged along a pair of short sides of the rectangular cover portion is less than a second area occupied by second foot segments among the foot segments arranged along a pair of long sides of the rectangular cover portion; and
a thermal interface material, wherein the rectangular cover portion of the lid is attached to the package through the thermal interface material.

11. The semiconductor device of claim 10 , wherein the package further comprises an interposer disposed between the packaging substrate and the semiconductor dies encapsulated by the insulating encapsulation, and the semiconductor dies are electrically connected to the packaging substrate through the interposer.

12. The semiconductor device of claim 10 , wherein the package comprises an integrated fanout structure assembled on packaging substrate.

13. The semiconductor device of claim 10 , wherein first stiffness adjustment grooves among the stiffness adjustment grooves are arranged along the pair of short sides of the rectangular cover portion, and second stiffness adjustment grooves among the stiffness adjustment grooves are arranged along the pair of long sides of the rectangular cover portion.

14. The semiconductor device of claim 13 , wherein a first extending direction of the first stiffness adjustment grooves is substantially paralleled with the pair of long sides of the rectangular cover portion, a second extending direction of the second stiffness adjustment grooves is substantially paralleled with the pair of short sides of the rectangular cover portion, and a first maximum width of the first stiffness adjustment grooves is greater than a second maximum width of the second stiffness adjustment grooves.

15. The semiconductor device of claim 13 , wherein a first depth of the first stiffness adjustment grooves is substantially equal to or greater than a second depth of the second stiffness adjustment grooves.

16. The semiconductor device of claim 10 , wherein the rectangular cover portion further comprises a ring-shaped indentation defining an attachment portion of the rectangular cover portion, and the attachment portion is in contact with the thermal interface material.

17. The semiconductor device of claim 10 , wherein the rectangular cover portion further comprises a protruding attachment portion, and the protruding attachment portion protrudes toward the package and is in contact with the thermal interface material.

18. A semiconductor device, comprising:
a package comprising a packaging substrate, semiconductor dies and an insulating encapsulation, wherein the semiconductor dies are disposed on and electrically connected to the packaging substrate, and the insulating encapsulation encapsulates the semiconductor dies;
a lid disposed on the packaging substrate, the lid comprising a cover portion and foot portion extending from the cover portion to the package, wherein the cover portion comprises an inner surface, an outer surface opposite to the inner surface, and stiffness adjustment grooves distributed on the outer surface, wherein the inner surface is between the package and the outer surface; and
a thermal interface material adhered with the inner surface of the cover portion of the lid and the package.

19. The semiconductor device of claim 18 , wherein the cover portion comprises a rectangular cover portion having a pair of short sides and a pair of long sides, and an extending direction of the stiffness adjustment grooves are substantially paralleled with the pair of short sides of the rectangular cover portion.

20. The semiconductor device of claim 19 , wherein the stiffness adjustment grooves extend from a first

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Wensen
• Shen Yih-Ting
• Li Jia-Syuan
• Chen Tsung-Yu

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W76/63

  characterised by their shape or disposition, e.g. between cap and walls of a container · CPC title

• H10W76/10

  Containers or parts thereof · CPC title