Display device

US12354550B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12354550-B2
Application numberUS-202418758335-A
CountryUS
Kind codeB2
Filing dateJun 28, 2024
Priority dateJul 5, 2023
Publication dateJul 8, 2025
Grant dateJul 8, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display device includes pixels arranged in rows and columns, a scan driver, and a read-out circuit, wherein the read-out circuit is configured to read-out electrical properties of a pixel through the read-out line. The first pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first organic light-emitting diode connected between a second electrode of the seventh transistor and a ground node to which a ground voltage is applied, a second organic light-emitting diode between the second electrode of the eighth transistor and the ground node, and a third organic light-emitting diode connected between the second electrode of the ninth transistor and the ground node.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising: pixels arranged in rows and columns; a scan driver connected to the rows of the pixels, wherein a first row of the rows of the pixels is connected to the scan driver through a scan line, a first emission control line, a second emission control line, a third emission control line, a fourth emission control line, an initialization line, and a read-out control line; a data driver connected to the columns of the pixels, wherein a first column of the columns of the pixels is connected to the scan driver through a data line; and a read-out circuit connected to the columns of the pixels and configured to read-out electrical properties of the pixels through a read-out line, wherein the first column is connected to the read-out circuit through the read-out line, wherein a first pixel of the pixels comprises: a first transistor comprising a first electrode connected to a first node, a second electrode connected to a third node, and a gate connected to a second node; a second transistor comprising a first electrode connected to the data line, a second electrode connected to the first node, and a gate connected to the scan line; a third transistor comprising a first electrode connected to the second node, a second electrode connected to the third node, and a gate connected to the scan line; a fourth transistor comprising a first electrode connected to a power node configured to supply a power supply voltage, a second electrode connected to the first node, and a gate connected to the first emission control line; a fifth transistor comprising a first electrode connected to the read-out line, a second electrode connected to the second node, and a gate connected to the initialization line; a sixth transistor comprising a first electrode connected to the read-out line, a second electrode connected to the third node, and a gate connected to the read-out control line; a seventh transistor comprising a first electrode connected to the third node, a second electrode, and a gate connected to the second emission control line; an eighth transistor comprising a first electrode connected to the third node, a second electrode, and a gate connected to the third emission control line; a ninth transistor comprising a first electrode connected to the third node, a second electrode, and a gate connected to the fourth emission control line; a capacitor connected to the first node and the second node; a first organic light-emitting diode connected between the second electrode of the seventh transistor and a ground node; a second organic light-emitting diode between the second electrode of the eighth transistor and the ground node; and a third organic light-emitting diode connected between the second electrode of the ninth transistor and the ground node. 2. The display device of claim 1 , wherein the scan driver is configured to, in a reset section of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an active level through the initialization line, output a read-out control signal at an inactive level through the read-out control line, output a first emission control signal at an active level through the first emission control line, output a second emission control signal at an inactive level through the second emission control line, output a third emission control signal at an inactive level through the third emission control line, and output a fourth emission control signal at an inactive level through the fourth emission control line. 3. The display device of claim 1 , wherein the scan driver is configured to, in a program section of the first pixel, output a scan signal at an active level through the scan line, output an initialization signal at an inactive level through the initialization line, output a read-out control signal at an inactive level through the read-out control line, output a first emission control signal at an inactive level through the first emission control line, output a second emission control signal at an inactive level through the second emission control line, output a third emission control signal at an inactive level through the third emission control line, and output a fourth emission control signal at an inactive level through the fourth emission control line. 4. The display device of claim 1 , wherein the scan driver is configured to, in a hold section of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an inactive level through the initialization line, output a read-out control signal at an inactive level through the read-out control line, output a first emission control signal at an inactive level through the first emission control line, output a second emission control signal at an inactive level through the second emission control line, output a third emission control signal at an inactive level through the third emission control line, and output a fourth emission control signal at an inactive level through the fourth emission control line. 5. The display device of claim 1 , wherein the scan driver is configured to, in a first emission section of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an inactive level through the initialization line, output a read-out control signal at an inactive level through the read-out control line, output a first emission control signal at an active level through the first emission control line, output a second emission control signal at an active level through the second emission control line, output a third emission control signal at an inactive level through the third emission control line, and output a fourth emission control signal at an inactive level through the fourth emission control line. 6. The display device of claim 1 , wherein the scan driver is configured to, in a second emission section of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an inactive level through the initialization line, output a read-out control signal at an inactive level through the read-out control line, output a first emission control signal at an active level through the first emission control line, output a second emission control signal at an inactive level through the second emission control line, output a third emission control signal at an active level through the third emission control line, and output a fourth emission control signal at an inactive level through the fourth emission control line. 7. The display device of claim 1 , wherein the scan driver is configured to, in a third emission section of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an inactive level through the initialization line, output a read-out control signal at an inactive level through the read-out control line, output a first emission control signal at an active level through the first emission control line, output a second emission control signal at an inactive level through the second emission control line, output a third emission control signal at an inactive level through the third emission control line, and output a fourth emission control signal at an active level through the fourth emission control line. 8. The display device of claim 1 , wherein the scan driver is configured to, in a first read-out section of the first pixel, output a scan signal at an inactive level through the scan line, output an initialization signal at an inactive level through the initialization line, output a read-out control signal at an active level through the read-out control lin

Assignees

Inventors

Classifications

  • forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

  • for control of overall brightness · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

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What does patent US12354550B2 cover?
A display device includes pixels arranged in rows and columns, a scan driver, and a read-out circuit, wherein the read-out circuit is configured to read-out electrical properties of a pixel through the read-out line. The first pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth t…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3266. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).