Pixel structure and driving method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-2016155385-A1
Application number	US-201414778848-A
Country	US
Kind code	A1
Filing date	Oct 11, 2014
Priority date	Jul 7, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

Provided are a pixel structure and driving method thereof, and a display apparatus. The pixel structure comprises a plurality of pixel units and compensation units corresponding to the pixel units. Each of the pixel units comprises two adjacent pixel circuits which are a first pixel circuit and a second pixel circuit. The first pixel circuit comprises a first driving transistor (DTFT 1 ) and a first display device (OLED 1 ), and the second pixel circuit comprises a second driving transistor (DTFT 2 ) and a second display device (OLED 2 ), wherein the first pixel circuit and the second pixel circuit share the compensation unit and are controlled by a same data line (Data). The compensation unit is configured to adjust a gate voltage of the first driving transistor (DTFT 1 ) in the first pixel circuit to eliminate the influence of the threshold voltage of the first driving transistor (DTFT 1 ) on the driving current of the first display device (OLED 1 ), and to adjust a gate voltage of the second driving transistor (DTFT 2 ) in the second pixel circuit to eliminate the influence of the threshold voltage of the second driving transistor (DTFT 2 ) on the driving current of the second display device (OLED 2 ). The pixel structure can reduce the pixel size and obtain higher resolution.

First claim

1 . A pixel structure comprising a plurality of pixel units, wherein the pixel structure further comprises compensation units corresponding to the pixel units, each of the pixel units comprises two adjacent pixel circuits which are a first pixel circuit and a second pixel circuit, the first pixel circuit comprises a first driving transistor and a first display device, the second pixel circuit comprises a second driving transistor and a second display device, and the first pixel circuit and the second pixel circuit share the compensation unit and are controlled by a same data line;
the compensation unit is configured to adjust a gate voltage of the first driving transistor in the first pixel circuit to eliminate the influence of the threshold voltage of the first driving transistor on the driving current of the first display device, and to adjust a gate voltage of the second driving transistor in the second pixel circuit to eliminate the influence of the threshold voltage of the second driving transistor on the driving current of the second display device.

2 . The pixel structure according to claim 1 , wherein the compensation unit comprises a first switch transistor, a second switch transistor, a third switch transistor, a fourth switch transistor, a fifth switch transistor, a sixth switch transistor, a seventh switch transistor, an eighth switch transistor, a ninth switch transistor, a tenth switch transistor, a first storage capacitor, and a second storage capacitor;
a gate of the first switch transistor is connected to a gate of the second switch transistor, a gate of the seventh transistor, and a first light emitting control line, a source of the first switch transistor is connected to a source of the second switch transistor and a first reference voltage source, and a drain of the first switch transistor is connected to a source of the fourth switch transistor and a source of the first driving transistor; the gate of the second switch transistor is connected to a gate of the eighth switch transistor, a drain of the second switch transistor is connected to a source of the fifth switch transistor and a source of the second driving transistor; a gate of the third switch transistor is connected to a gate of the fourth switch transistor and a first scan line, a source of the third switch transistor is connected to a data line, a drain of the third switch transistor is connected to a second terminal of the first storage capacitor and a source of the seventh switch transistor; a drain of the fourth switch transistor is connected to a first terminal of the first storage capacitor and a gate of the first driving transistor; a gate of the fifth switch transistor is connected to a gate of the sixth switch transistor and a second scan line, a source and a drain of the fifth switch transistor are connected to a first terminal of the second storage capacitor and a gate of the second driving transistor; a source of the sixth switch transistor is connected to the data line, a drain of the sixth switch transistor is connected to a second terminal of the second storage capacitor and a drain of the eighth switch transistor; a drain of the seventh switch transistor is connected to a source of the ninth switch transistor, a drain of the first driving transistor, and a first terminal of the first display device, and a second terminal of the first display device is grounded; a source of the eighth switch transistor is connected to a source of the tenth switch transistor, a drain of the second driving transistor, and a first terminal of the second display device, and a second terminal of the second display device is grounded; a gate of the ninth switch transistor is connected to a gate of the tenth switch transistor and the second scan line, and a drain of the ninth switch transistor is grounded; a drain of the tenth switch transistor is grounded.

3 . The pixel structure according to claim 2 , wherein the first switch transistor, the second switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor, the sixth switch transistor, the seventh switch transistor, the eighth switch transistor, the ninth switch transistor, the tenth switch transistor, the first driving transistor, the second driving transistor are all N type thin film transistors.

4 . The pixel structure according to claim 1 , wherein the compensation unit comprises an eleventh switch transistor, a twelfth switch transistor, a thirteenth switch transistor, a fourteenth switch transistor, a fifteenth switch transistor, a sixteenth switch transistor, a seventeenth switch transistor, an eighteenth switch transistor, a nineteenth switch transistor, a third storage capacitor, and a fourth storage capacitor;
a gate of the eleventh switch transistor is connected to a second light emitting control line, a source of the eleventh switch transistor is connected to the first reference voltage source, a drain of the eleventh switch transistor is connected to the source of the first driving transistor and the source of the second driving transistor; a gate of the twelfth switch transistor is connected to a third scan line, a source of the twelfth switch transistor is connected to the data line, a drain of the twelfth switch transistor is connected to a source of the thirteenth switch transistor and a first terminal of the third storage capacitor; a gate of the thirteenth switch transistor is connected to a gate of the fourteenth switch transistor and a third light emitting control line, and a drain of the thirteenth switch transistor is grounded; a source of the fourteenth switch transistor is connected to a first terminal of the fourth storage capacitor and a drain of the fifteenth switch transistor, and a drain of the fourteenth switch transistor is grounded; a gate of the fifteenth switch transistor is connected to a fourth scan line, and a source of the fifteenth switch transistor is connected to the data line; a gate of the sixteenth switch transistor is connected to a gate of the seventeenth switch transistor and a third light emitting control line, a source of the sixteenth switch transistor is connected to the gate of the first driving transistor and a second terminal of the third storage capacitor, a drain of the sixteenth switch transistor is connected to the drain of the first driving transistor and a source of the eighteenth switch transistor; a source of the seventeenth switch transistor is connected to the gate of the second driving transistor and a second terminal of the fourth storage capacitor, a drain of the seventeenth switch transistor is connected to the drain of the second driving transistor and a source of the nineteenth switch transistor; a gate of the eighteenth switch transistor is connected to a gate of the nineteenth switch transistor and a fourth light emitting control line, a drain of the eighteenth switch transistor is connected to the first terminal of the first display device, and the second terminal of the first display device is grounded; a drain of the nineteenth switch transistor is connected to the first terminal of the second display device, and the second terminal of the second display device is grounded.

5 . The pixel structure according to claim 4 , wherein the pixel structure further comprises a capacitive touch unit and a light sensitive type touch unit connected to the compensation unit;
the capacitive touch unit is configured to generate a corresponding electrical signal according to a touch signal and realize touch and control by a finger; the light sensitive type touch unit is configured to generate a corresponding electrical signal according to an illumination intensity signal and realize touch and control by a laser pen.

6 . The pixel structure according to claim 5

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics

Inventors

• Yang Shengji

Classifications

• G06F3/03545

  Pens or stylus · CPC title

• G09G3/3258 Primary

  with pixel circuitry controlling the voltage across the light-emitting element · CPC title

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/042

  by opto-electronic means · CPC title

• G09G2320/043

  Preventing or counteracting the effects of ageing · CPC title