Electronic display device having plurality of openings in common electrode overlapping transmission portions of blocking pattern, and method for manufacturing the same

US12349586B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12349586-B2
Application numberUS-202117379429-A
CountryUS
Kind codeB2
Filing dateJul 19, 2021
Priority dateJul 21, 2020
Publication dateJul 1, 2025
Grant dateJul 1, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device includes: a display panel including a display region including a first display region and a second display region having a higher transmittance than the first display region and an electronic module below the second display region of the display panel, wherein the display panel includes: a base layer; a plurality of first pixel electrodes on the base layer and in the first display region; a plurality of second pixel electrodes on the base layer and in the second display region; a common electrode on the plurality of first pixel electrodes and the plurality of second pixel electrodes and in which a plurality of openings are defined; and a blocking pattern spaced apart from the common electrode with the plurality of second pixel electrodes interposed therebetween and having a plurality of transmission portions overlapping the plurality of openings.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic device comprising: a display panel including a display region including a first display region and a second display region, the second display region having a higher transmittance than the first display region; and an electronic module below the second display region of the display panel, wherein the display panel includes: a base layer; a plurality of first pixel electrodes on the base layer and in the first display region; a plurality of second pixel electrodes on the base layer and in the second display region; a common electrode on the plurality of first pixel electrodes and the plurality of second pixel electrodes and in which a plurality of openings are defined; and a blocking pattern spaced apart from the common electrode with the plurality of second pixel electrodes interposed therebetween and in which a plurality of transmission portions overlapping the plurality of openings are defined, wherein both the plurality of second pixel electrodes and the plurality of openings overlap in the plan view, the electronic module. 2. The electronic device of claim 1 , wherein the display panel further comprises: a plurality of first pixel circuits electrically connected to the plurality of first pixel electrodes, respectively; and a plurality of second pixel circuits electrically connected to the plurality of second pixel electrodes, respectively, wherein each of the plurality of first pixel circuits and the plurality of second pixel circuits includes a transistor including a gate, an active region, a source, and a drain, and a capacitor including a first electrode electrically connected to the transistor and a second electrode facing the first electrode. 3. The electronic device of claim 2 , wherein the blocking pattern comprises a first blocking pattern and a second blocking pattern on the first blocking pattern, wherein: the first blocking pattern is on a same layer as that of the gate, and includes a same material as that of the gate, and the second blocking pattern is on a same layer as that of the second electrode, and includes a same material as that of the second electrode. 4. The electronic device of claim 3 , wherein the blocking pattern further comprises a third blocking pattern below the first blocking pattern. 5. The electronic device of claim 4 , wherein the display panel further comprises a barrier layer on the base layer and a buffer layer on the barrier layer, wherein: the barrier layer includes a first sub-barrier layer on the base layer and a second sub-barrier layer on the first sub-barrier layer, and the third blocking pattern is between the barrier layer and the buffer layer, or is between the first sub-barrier layer and the second sub-barrier layer. 6. The electronic device of claim 4 , wherein, in the first blocking pattern, the second blocking pattern, and the third blocking pattern, a plurality of first transmission portions, a plurality of second transmission portions, and a plurality of third transmission portions which overlap the plurality of openings of the common electrode are respectively defined. 7. The electronic device of claim 2 , wherein the blocking pattern is on a same layer as that of either the gate or the second electrode and includes a same material as that of either the gate or the second electrode. 8. The electronic device of claim 2 , wherein the display panel further comprises a peripheral region adjacent to the display region, and wherein the plurality of first pixel circuits are in the first display region, and the plurality of second pixel circuits are in the peripheral region. 9. The electronic device of claim 2 , wherein the display panel further comprises a plurality of connection lines electrically connecting the plurality of second pixel electrodes and the plurality of second pixel circuits, respectively, and each of the plurality of connection lines includes a transparent conductive material. 10. The electronic device of claim 2 , wherein the display region further comprises a third display region between the first display region and the second display region, and the plurality of second pixel circuits are in the third display region. 11. The electronic device of claim 10 , wherein the display panel further comprises a plurality of third pixel electrodes on the base layer and in the third display region and a plurality of third pixel circuits in the third display region and electrically connected to the plurality of third pixel electrodes, respectively, wherein a first number of first pixel electrodes in a first region among the plurality of first pixel electrodes is greater than each of a second number of second pixel electrodes in a second region having a same size as that of the first region among the plurality of second pixel electrodes and a third number of third pixel electrodes in a third region having the same size as that of the first region among the plurality of third pixel electrodes. 12. The electronic device of claim 1 , wherein the plurality of openings and the plurality of transmission portions are in the second display region. 13. The electronic device of claim 1 , wherein, in the plan view, the plurality of transmission portions and the plurality of openings are spaced apart from the plurality of second pixel electrodes. 14. An electronic device comprising: a display panel having a display region is defined; and an electronic module below the display region of the display panel, wherein the display panel includes: a light emitting element having a pixel electrode in the display region, a light emitting layer on the pixel electrode, and a common electrode on the light emitting layer; a blocking pattern below the light emitting element having a transmission portion in a region spaced apart from the pixel electrode in a plan view; a pixel circuit spaced apart from the pixel electrode and electrically connected to the light emitting element; and a connection line electrically connecting the pixel circuit and the pixel electrode and including a transparent conductive material, wherein, in the plan view, an opening through the common electrode is overlapping the transmission portion, wherein both the light emitting element and the opening overlap in the plan view, with the electronic module. 15. The electronic device of claim 14 , wherein the display panel further comprises a peripheral region adjacent to the display region, and wherein the pixel circuit is in the peripheral region. 16. The electronic device of claim 14 , wherein the pixel circuit comprises a transistor including a gate, an active region, a source, and a drain, and a capacitor including a first electrode electrically connected to the transistor and a second electrode facing the first electrode, and the blocking pattern comprises a first blocking pattern and a second blocking pattern on the first blocking pattern, wherein the first blocking pattern is on a same layer as that of the gate, and includes a same material as that of the gate, and the second blocking pattern is on a same layer as that of the second electrode, and includes a same material as that of the second electrode.

Assignees

Inventors

Classifications

  • Arrangements for improving contrast, e.g. preventing reflection of ambient light · CPC title

  • Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

  • Active-matrix OLED [AMOLED] displays · CPC title

  • H10K50/865Primary

    comprising light absorbing layers, e.g. light-blocking layers · CPC title

  • using coherent electromagnetic radiation, e.g. laser annealing · CPC title

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What does patent US12349586B2 cover?
An electronic device includes: a display panel including a display region including a first display region and a second display region having a higher transmittance than the first display region and an electronic module below the second display region of the display panel, wherein the display panel includes: a base layer; a plurality of first pixel electrodes on the base layer and in the first …
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K50/865. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 01 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).