Thin film transistor array panel and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9257563-B2
Application number	US-201313798811-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Sep 21, 2012
Publication date	Feb 9, 2016
Grant date	Feb 9, 2016

Abstract

A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.

First claim

What is claimed is:

1. A thin film transistor array panel, comprising:
a substrate,
a thin film transistor on the substrate, the thin film transistor comprising:
a gate electrode which receives a gate signal,
a gate insulating layer on the gate electrode,
a semiconductor layer on the gate insulating layer,
a source electrode and a drain electrode which receives a data voltage, on the semiconductor layer and facing each other, and
a floating metal layer disposed between the drain electrode and the source electrode, the floating metal layer electrically floating,

a pixel electrode connected to the drain electrode of the thin film transistor through a contact hole, the pixel electrode which receives the data voltage from the drain electrode to which it is connected, and
a passivation layer covering the thin film transistor to which the pixel electrode is connected.

2. The thin film transistor array panel of claim 1 , wherein:
the semiconductor layer comprises a channel portion, and
the floating metal layer overlaps the channel portion of the semiconductor layer.

3. The thin film transistor array panel of claim 2 , wherein:
the floating metal layer is directly on the semiconductor layer.

4. The thin film transistor array panel of claim 3 , wherein:
the floating metal layer is in a same layer as the source electrode and the drain electrode.

5. The thin film transistor array panel of claim 4 , wherein:
the floating metal layer is island-shaped.

6. The thin film transistor array panel of claim 5 , wherein:
an electrical current moving path in the semiconductor layer has a “W” shape.

7. The thin film transistor array panel of claim 2 , wherein the thin film transistor further comprises:
a single, unitary etching prevention layer between the floating metal layer and the semiconductor layer, elongated between the source and drain electrodes of the thin film transistor,
wherein
the single, unitary etching prevention layer covers a channel region of the semiconductor layer, and
an upper surface of the etching prevention layer contacts the passivation layer between the source electrode and the floating metal layer or between the drain electrode and the floating metal layer.

8. The thin film transistor array panel of claim 7 , wherein:
the source electrode and the drain electrode overlap opposing edges of the elongated single, unitary etching prevention layer which is between the floating metal layer and the semiconductor layer.

9. The thin film transistor array panel of claim 8 , wherein:
the floating metal layer is in a same layer as the source electrode and the drain electrode.

10. The thin film transistor array panel of claim 9 , wherein:
the floating metal layer is island-shaped.

11. The thin film transistor array panel of claim 10 , wherein:
an electrical current moving path in the semiconductor layer has a “W” shape.

12. The thin film transistor array panel of claim 1 , wherein:
the semiconductor layer comprises an oxide semiconductor.

13. The thin film transistor array panel of claim 12 , wherein:
the floating metal layer comprises a material having a Fermi level higher than a Fermi level of the semiconductor layer.

14. A method of manufacturing a thin film transistor array panel, the method comprising:
providing a thin film transistor, the thin film transistor comprising:
a gate electrode which receives a gate signal from a gate line, on a substrate,
a gate insulating layer on the gate electrode,
an oxide semiconductor layer on the gate insulating layer,
a source electrode and a drain electrode which is extended from a data line which transmits a data voltage, facing each other on the oxide semiconductor layer, and
a floating metal layer between the source electrode and the drain electrode, the floating metal layer electrically floating,

providing a pixel electrode connected to the drain electrode of the thin film transistor through a contact hole, the pixel electrode receiving the data voltage from the drain electrode to which it is connected, and
providing a passivation layer covering the thin film transistor to which the pixel electrode is connected.

15. The method of manufacturing a thin film transistor array panel of claim 14 , wherein:
the oxide semiconductor layer comprises a channel portion, and
the floating metal layer overlaps the channel portion of the oxide semiconductor layer.

16. The method of manufacturing a thin film transistor array panel of claim 15 , wherein:
the floating metal layer is directly on the oxide semiconductor layer.

17. The method of manufacturing a thin film transistor array panel of claim 16 , wherein:
the providing the source electrode, the drain electrode and the floating metal layer comprises forming the floating metal layer during a same process as forming the source electrode and the drain electrode.

18. The method of manufacturing a thin film transistor array panel of claim 15 , wherein the thin film transistor further comprises:
a single, unitary etching prevention layer between the floating metal layer and the oxide semiconductor layer, elongated between the source and drain electrodes of the thin film transistor, the elongated single, unitary etching prevention layer exposed between the source electrode and the drain electrode, and the floating metal layer, respectively.

19. The method of manufacturing a thin film transistor array panel of claim 18 , wherein:
the source electrode and the drain electrode overlap opposing edges of the elongated single, unitary etching prevention layer which is between the floating metal layer and the semiconductor layer.

20. The thin film transistor array panel of claim 1 , wherein:
portions of the electrically floating metal layer disposed between the drain electrode and the source electrode respectively define:
a drain portion of the thin film transistor through which electrical current flows from the source electrode to the drain portion, and
a source portion of the thin film transistor through which electrical current flows from the source portion to the drain electrode.

Assignees

• Samsung Display Co Ltd
• Univ Kookmin Ind Acad Coop Found

Inventors

• Ahn Byung Du
• Kim Jung Hwa
• Lim Ji Hun
• Lee Je Hun
• Kim Dae Hwan
• Jung Hyun Kwang

Classifications

• H10D30/6755 Primary

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D30/6756

  Amorphous oxide semiconductors · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D30/6729

  characterised by the electrodes · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title