Low force liquid metal interconnect solutions

US12349303B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12349303-B2
Application numberUS-202318112953-A
CountryUS
Kind codeB2
Filing dateFeb 22, 2023
Priority dateJun 15, 2020
Publication dateJul 1, 2025
Grant dateJul 1, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

First claim

Opening claim text (preview).

What is claimed is: 1. An electronic package, comprising: a package substrate having a first surface and a second surface opposite from the first surface; and an interface on the second surface of the package substrate, wherein the interface comprises: a first layer, wherein the first layer comprises a plurality of wells; a material comprising gallium within the plurality of wells; and a second layer over the plurality of wells, wherein the second layer is vertically overlapping with the material. 2. The electronic package of claim 1 , wherein the package substrate comprises a plurality of pads on the second surface, wherein individual ones of the plurality of pads are aligned with individual ones of the plurality of wells. 3. The electronic package of claim 1 , wherein the second layer confines the material comprising gallium to the plurality of wells. 4. The electronic package of claim 1 , wherein the second layer comprises a self-sealing material. 5. The electronic package of claim 1 , wherein the second layer comprises one or more of a closed cell foam, an open cell foam, a nonwoven mesh, a woven mesh, or an elastic material. 6. The electronic package of claim 5 , wherein the second layer is a laminated stack. 7. The electronic package of claim 5 , wherein the second layer is a composite material. 8. The electronic package of claim 1 , wherein the plurality of wells comprises approximately 7,000 or more wells. 9. The electronic package of claim 1 , further comprising: a socket attached to the package substrate, wherein the socket comprises: a socket substrate; and a plurality of pins extending away from the socket substrate, wherein individual ones of the plurality of pins are inserted into individual ones of the plurality of wells. 10. An electronic package, comprising: a package substrate having a first surface and a second surface opposite from the first surface; a die on the first surface; and an interface on the second surface of the package substrate, wherein the interface comprises: a first layer, wherein the first layer comprises first and second wells; a material comprising gallium within the first and second wells; and a second layer over the first and second wells, wherein the second layer is vertically overlapping with the material. 11. The electronic package of claim 10 , wherein the package substrate comprises a plurality of pads on the second surface, wherein individual ones of the plurality of pads are aligned with individual ones of the plurality of wells. 12. The electronic package of claim 10 , wherein the second layer confines the material comprising gallium to the plurality of wells. 13. The electronic package of claim 10 , wherein the second layer comprises a self-sealing material. 14. The electronic package of claim 10 , wherein the second layer comprises one or more of a closed cell foam, an open cell foam, a nonwoven mesh, a woven mesh, or an elastic material. 15. The electronic package of claim 14 , wherein the second layer is a laminated stack. 16. The electronic package of claim 14 , wherein the second layer is a composite material. 17. The electronic package of claim 10 , wherein the plurality of wells comprises approximately 7,000 or more wells. 18. The electronic package of claim 10 , further comprising: a socket attached to the package substrate, wherein the socket comprises: a socket substrate; and a plurality of pins extending away from the socket substrate, wherein individual ones of the plurality of pins are inserted into individual ones of the plurality of wells. 19. An electronic system, comprising: a board; and an electronic package electrically coupled to the board, wherein the electronic package comprises: a package substrate having a first surface and a second surface opposite from the first surface; a die on the first surface; and an interface on the second surface of the package substrate, wherein the interface comprises: a first layer, wherein the first layer comprises first and second wells; a material comprising gallium within the first and second wells; and a second layer over the first and second wells, wherein the second layer is vertically overlapping with the material. 20. The electronic system of claim 19 , wherein the package substrate comprises a plurality of pads on the second surface, wherein individual ones of the plurality of pads are aligned with individual ones of the plurality of wells.

Assignees

Inventors

Classifications

  • Liquid fillings · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • Conductive materials thereof · CPC title

  • characterised by their shape, e.g. having conical or cylindrical projections · CPC title

  • H10W76/153Primary

    having interconnections in passages through the insulating or insulated base · CPC title

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What does patent US12349303B2 cover?
Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W76/153. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 01 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).