Semiconductor chip, debug system, and synchronization method

Patent metadata

Field	Value
Publication number	US-12346235-B2
Application number	US-202318482241-A
Country	US
Kind code	B2
Filing date	Oct 6, 2023
Priority date	Nov 21, 2022
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A semiconductor chip includes a first common marker generating circuit and a second common marker generating circuit. The first common marker generating circuit is configured to send a first request signal to the second common marker generating circuit, the first request signal requesting a common marker to be sent to a second trace memory, and to send the common marker to a first trace memory, when a second request signal is received from the second common marker generating circuit, the second request signal requesting the common marker to be sent to the first trace memory. The second common marker generating circuit is configured to send the common marker to the second trace memory and to send the second request signal to the first common marker generating circuit, if a second core is running a user program at a time when the first request signal is received.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a first common marker generating circuit configured to send a common marker to a first trace memory, the first trace memory being configured to store trace data from a first core and the common marker; and
a second common marker generating circuit configured to send the common marker to a second trace memory, the second trace memory being configured to store trace data from a second core and the common marker, the second core being different from the first core,
wherein the common marker allows synchronization between the trace data from the first core with the trace data from the second core,
wherein the first common marker generating circuit is configured to send, to the second common marker generating circuit, a first request signal while the first core is running a first user program, the first request signal requesting the second common marker generating circuit to send the common marker to the second trace memory,
wherein, upon receiving the first request signal from the first common marker generating circuit while the second core is running a second user program, the second common marker generating circuit is configured to i) send the common marker to the second trace memory and ii) send a second request signal to the first common marker generating circuit, the second request signal requesting the first common marker generating circuit to send the common marker to the second trace memory, and
wherein, upon receiving the second request signal from the second common marker generating circuit, the first common marker generating circuit is configured to send the common marker to the first trace memory.

2. The semiconductor chip according to claim 1 , wherein the first common marker generating circuit is configured to send the first request signal at regular intervals while the first core is running the first user program.

3. The semiconductor chip according to claim 2 ,
wherein the first common marker generating circuit includes:
a first counter configured to start counting when the first core starts to run the first user program; and
a counter setting register in which a counter value is set, and

wherein the first common marker generating circuit is configured to send the first request signal when a counter value of the first counter matches a counter value set in the counter setting register.

4. The semiconductor chip according to claim 3 , further comprising a clock selection circuit configured to select a clock, which is to be input to the first counter, from among a plurality of clocks.

5. The semiconductor chip according to claim 3 , wherein a memory size of the first trace memory and a memory size of the second trace memory are different from each other.

6. A debug system comprising:
the semiconductor chip according to claim 1 ; and
a host computer configured to display the trace data from the first core and the trace data from the second core in synchronization based on the common marker.

7. The debug system according to claim 6 , wherein the host computer is configured to display a screen on which a first graph indicating running time of a function on the first core and a second graph indicating running time of a function on the second core are synchronized based on the common marker.

8. A synchronization method using a semiconductor chip which includes i) a first common marker generating circuit configured to send a common marker to a first trace memory and ii) a second common marker generating circuit configured to send the common marker to a second trace memory, wherein the first trace memory is configured to store trace data from a first core and the common marker, wherein the second trace memory is configured to store trace data from a second core, wherein the second core is different from the first core, and wherein the common marker allows synchronize between the trace data from the first core with the trace data from the second core, the synchronization method comprising:
sending a first request signal from the first common marker generating circuit to the second common marker generating circuit while the first core is running a first user program, the first request signal requesting the second common marker generating circuit to send the common marker to the second trace memory;
if upon receiving the first request signal at the second common marker generating circuit from the first common marker generating circuit while the second core is running a second user program, i) sending the common marker from the second common marker generating circuit to the second trace memory and ii) sending a second request signal from the second common marker generating circuit to the first common marker generating circuit, the second request signal requesting the first common marker generating circuit to send the common marker to the first trace memory; and
upon receiving the second request signal from the second common marker generating circuit to the first common marker generating circuit-receives the second request signal, sending the common marker from the first common marker generating circuit to the first trace memory.

9. The synchronization method according to claim 8 , further comprising displaying the trace data from the first core and the trace data from the second core in synchronization based on the common marker.

Assignees

• Renesas Electronics Corp

Inventors

• Sasaki Hiroyuki
• Hatahara Hirofumi

Classifications

• G06F11/3476

  Data logging (G06F11/14, G06F11/2205 take precedence) · CPC title

• G06F11/323 Primary

  Visualisation of programs or trace data · CPC title

• G06F11/348 Primary

  Circuit details, i.e. tracer hardware · CPC title