Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-12342540-B2
Application number	US-202217728651-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Apr 25, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple with conductor material of the conductor tier by conductive material of a lowest of the conductive tiers. Insulating material of the insulative tier that is immediately-directly above the lowest conductive tier is directly against a top of the conductive material of the lowest conductive tier. The insulating material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, and carbon-doped insulative material. Other embodiments, including method, are disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a lower portion of a stack above a conductor tier, the lower portion comprising laterally-spaced memory-block regions, the lower portion comprising:
sacrificial first material in a lower-portion first tier;
horizontally-elongated lines in the lower-portion first tier that are individually laterally-between and along laterally-adjacent of the laterally-spaced memory-block regions, the horizontally-elongated lines comprising an insulative second material that is of different composition from that of the sacrificial first material, the insulative second material of the horizontally-elongated lines being everywhere spaced vertically above the conductor tier, the sacrificial first material of the lower-portion first tier being directly below bottoms of the horizontally-elongated lines and directly above the conductor tier;
a lower-portion second tier directly above the lower-portion first tier and comprising the insulative second material directly against the lower-portion first tier and directly above the horizontally-elongated lines; and
third material directly above and directly against the insulative second material that is directly against the lower-portion first tier and directly above the horizontally-elongated lines, the third material being of different composition from those of the first and second materials;

forming vertically-alternating first tiers and second tiers of an upper portion of the stack directly above the lower portion;
forming horizontally-elongated trenches into the stack that are individually between the laterally-adjacent memory-block regions and extend to the horizontally-elongated line directly therebelow;
through the horizontally-elongated trenches, etching away all of horizontally-elongated lines and etching only some of the insulative second material that is directly above and directly against the lower-portion first tier, the etching away of all of the horizontally-elongated lines exposing the sacrificial first material that was directly below the bottoms of the horizontally-elongated lines, the etching of only some of the insulative second material that is directly above and directly against the lower-portion first tier exposing the third material; and
through the horizontally-elongated trenches, etching the sacrificial first material selectively relative to the third material.

2. The method of claim 1 wherein the insulative second material of the horizontally-elongated lines is laterally-outward of opposing sides of core material of the horizontally-elongated lines that is of different composition from those of the first, second, and third materials.

3. The method of claim 1 wherein the sacrificial first material comprises polysilicon.

4. The method of claim 1 wherein the insulative second material comprises silicon dioxide.

5. The method of claim 1 wherein the third material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, carbon-doped insulative material, and carbon-doped polysilicon.

6. The method of claim 1 wherein,
the sacrificial first material comprises polysilicon;
the insulative second material comprises silicon dioxide; and
the third material comprises at least one of aluminum oxide, hafnium oxide, zirconium oxide, carbon-doped insulative material, and carbon-doped polysilicon.

7. The method of claim 1 wherein the third material comprises carbon-doped silicon nitride.

8. The method of claim 7 wherein the carbon-doped silicon nitride has carbon therein at 0.5 to 50.0 atomic percent.

9. The method of claim 8 wherein the carbon-doped silicon nitride has carbon therein at 1.0 to 10 atomic percent.

10. The method of claim 1 wherein the lower portion comprises another lower-portion second tier that is directly below the lower-portion first tier and directly below the insulative second material of the horizontally-elongated lines, the sacrificial first material being vertically between the another lower-portion second tier and the second material of the horizontally-elongated lines.

Assignees

• Micron Technology Inc

Inventors

• Wang Yiping
• Saxler Adam W
• Bilik Narula

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title