Semiconductor memory devices having closely spaced bit lines

Patent metadata

Field	Value
Publication number	US-10056404-B2
Application number	US-201614989955-A
Country	US
Kind code	B2
Filing date	Jan 7, 2016
Priority date	Aug 7, 2015
Publication date	Aug 21, 2018
Grant date	Aug 21, 2018

Abstract

The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate having an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
a memory cell array on the substrate;
a first page buffer under the memory cell array, the first page buffer being adjacent a first side of the memory cell array;
a second page buffer under the memory cell array, the second page buffer being adjacent a second side, opposite to the first side, of the memory cell array;
a plurality of bit lines that extend in the second direction to at least partly cross the memory cell array, the bit lines including:
a plurality of first bit lines that are electrically connected to the first page buffer; and
a plurality of second bit lines that are electrically connected to the second page buffer;

a plurality of first connection conductive lines that extend in the second direction, wherein the first connection conductive lines electrically connect respective ones of the first bit lines to the first buffer; and
a plurality of second connection conductive lines that extend in the second direction, wherein the second connection conductive lines electrically connect respective ones of the second bit lines to the second page buffer,
wherein the first bit lines and the second bit lines are alternately and repeatedly arranged in the first direction, and
wherein a first distance between adjacent ones of the first connection conductive lines is greater than a second distance between adjacent ones of the bit lines, and wherein a third distance between adjacent ones of the second connection conductive lines is greater than the second distance.

2. The semiconductor memory device of claim 1 , wherein an average width of a first of the first connection conductive lines in the first direction is greater than an average width in the first direction of a first of the first bit lines, and an average width of a first of the second connection conductive lines in the first direction is greater than an average width in the first direction of a first of the second bit lines.

3. The semiconductor memory device of claim 1 , wherein the substrate includes a first connection region, a second connection region and a circuit region therebetween, the memory cell array being disposed on the circuit region, and wherein the first bit lines extend onto the first connection region, and the second bit lines extend onto the second connection region.

4. The semiconductor memory device of claim 3 , wherein a maximum width of a first portion of a first of the first bit lines that is on the first connection region exceeds a maximum width of a second portion of the first of the first bit lines that crosses the memory cell array, and a maximum width of a first portion of a first of the second bit lines that is on the second connection region exceeds a maximum width of a second portion of the first of the second bit lines that crosses the memory cell array.

5. The semiconductor memory device of claim 3 , wherein a maximum width of a first portion of a first of the first connection conductive lines that is on the first connection region exceeds a maximum width of a second portion of the first of the first connection conductive lines that is under the memory cell array, and a maximum width of a first portion of a first of the second connection conductive lines that is on the second connection region, exceeds a maxim width of a second portion of the first of the second connection conductive lines that is under the memory cell array.

6. The semiconductor memory device of claim 1 , wherein the first of the first connection conductive lines extends a different distance in the second direction onto a first connection region than does a second of the first connection conductive lines that is adjacent to the first of the first connection conductive lines, and
wherein the first of the second connection conductive lines extends a different distance in the second direction onto a second connection region than does a second of the second connection conductive lines that is adjacent to the first of the second connection conductive lines.

7. The semiconductor memory device of claim 1 , wherein each of the first and second bit lines includes a first conductive material, and each of the first and second connection conductive lines includes a second conductive material that has a melting point that is higher than a melting point of the first conductive material.

8. The semiconductor memory device of claim 7 , wherein the first conductive material includes copper (Cu) or aluminum (Al) and the second conductive material includes tungsten (W).

9. A semiconductor memory device, comprising:
a substrate having a circuit region and first and second connection regions on opposed sides of the circuit region, the substrate including an upper surface that extends in a first direction and in a second direction that is perpendicular to the first direction;
a memory cell array on the substrate;
a plurality of bit lines that extend in the second direction to at least partially cross the circuit region, the bit lines spaced apart from each other in the first direction;
a plurality of connection conductive lines that extend in the second direction and that are electrically connected to respective ones of the bit lines; and
a page buffer circuit that includes a first page buffer and a second page buffer, and wherein the connection conductive lines comprise first connection conductive lines and second connection conductive lines,
wherein an average width in the first direction of a first of the connection conductive lines is greater than an average width in the first direction of the one of the bit lines to which the first of the connection conductive lines is electrically connected, and
wherein the bit lines comprise first bit lines that are electrically connected to the first page buffer by respective ones of the first connection conductive lines and second bit lines that are electrically connected to the second page buffer by respective ones of the second connection conductive lines, and wherein the first bit lines and the second bit lines are alternately and repeatedly arranged in the first direction.

10. The semiconductor memory device of claim 9 , further comprising:
a plurality of first lower contacts and a plurality of second lower contacts that extend in a third direction that is perpendicular to the first direction and to the second direction; and
a plurality of first connection contacts and a plurality of second connection contacts that extend in the third direction,
wherein each first connection conductive line directly contacts a respective one of the first lower contacts and a respective one of the first connection contacts, and
wherein each second connection conductive line directly contacts a respective one of the second lower contacts and a respective one of the second connection contacts.

11. The semiconductor memory device of claim 10 , wherein each bit line has a first end portion that is adjacent a first side of the memory cell array and a second end portion that is adjacent a second side of the memory cell array, and wherein the first end portions of the first bit lines directly contact respective ones of the first connection contacts and the second end portions of the second bit lines directly contact respective ones of the second connection contacts.

12. The semiconductor memory device of claim 11 , wherein the first end portions of the first bit lines have an expanded width in the first direction.

13. The semiconductor memory device of claim 10 , wherein po

Assignees

• Lee Jaeduk
• Park Youngwoo
• Samsung Electronics Co Ltd

Inventors

• Lee Jaeduk
• Park Youngwoo

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H01L27/11573

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title