Multi-faced molded semiconductor package and related methods

Patent metadata

Field	Value
Publication number	US-12341014-B2
Application number	US-202217658071-A
Country	US
Kind code	B2
Filing date	Apr 5, 2022
Priority date	Aug 17, 2017
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of a die included in each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a die comprising a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side, the first side of the die comprising a plurality of electrical contacts comprising a plurality of bumps;
a first mold compound covering the first side of the die, the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die, wherein the plurality of bumps extend through a plurality of openings in the first mold compound;
a solder resist layer directly coupled to the first side of the die;
a passivation layer coupled between the solder resist layer and the first mold compound; and
one of a second mold compound or a laminate resin covering the sixth side of the die;
wherein the first mold compound is a single and continuous mold compound;
wherein the plurality of bumps are directly coupled to and over an outer surface of the first mold compound; and
wherein the plurality of bumps are configured to contact an external device.

2. The package of claim 1 , wherein the sixth side opposes the first side.

3. The package of claim 1 , wherein a perimeter of the first side of the die comprises one of an octagon or a rounded rectangle.

4. The package of claim 1 , wherein the first mold compound is anchored to the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die through a plurality of ridges formed in the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die.

5. The package of claim 1 , wherein the plurality of electrical contacts comprise one of a combination of nickel, gold, and aluminum or a combination of tin, silver, and copper.

6. The package of claim 1 , wherein the passivation layer comprises a polyimide.

7. A semiconductor package, comprising:
a die comprising a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side, the first side of the die comprising a plurality of electrical contacts comprising a plurality of bumps;
a first mold compound covering the first side of the die, the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die, wherein the plurality of bumps extend through a plurality of openings in the first mold compound;
a solder resist layer directly coupled to the first side of the die;
an interlayer coupled between the solder resist layer and the first mold compound; and
one of a second mold compound or a laminate resin covering the sixth side of the die;
wherein the first mold compound is a single and continuous mold compound;
wherein the plurality of bumps is directly coupled to and over an outer surface of the first mold compound; and
wherein the plurality of bumps are configured to make contact with an external device.

8. The package of claim 7 , wherein the sixth side opposes the first side.

9. The package of claim 7 , wherein a perimeter of the first side of the die comprises one of an octagon or a rounded rectangle.

10. The package of claim 7 , wherein the first mold compound is anchored to the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die through a plurality of ridges formed in the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die.

11. The package of claim 7 , wherein the plurality of electrical contacts comprise one of a combination of nickel, gold, and aluminum or a combination of tin, silver, and copper.

12. A semiconductor package, comprising:
a die comprising a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side, the first side of the die comprising a plurality of electrical contacts comprising a plurality of bumps;
a mold compound covering the first side of the die, the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die, wherein the plurality of bumps extend through a plurality of openings in the mold compound;
a solder resist layer directly coupled to the first side of the die; and
one of a passivation layer or an interlayer coupled between the solder resist layer and the mold compound;
wherein the mold compound is a single and continuous mold compound;
wherein the plurality of bumps is directly coupled to and over an outer surface of the mold compound; and
wherein the plurality of bumps is configured to make contact with an external device.

13. The package of claim 12 , wherein the sixth side opposes the first side.

14. The package of claim 12 , wherein a perimeter of the first side of the die comprises one of an octagon or a rounded rectangle.

15. The package of claim 12 , wherein the mold compound is anchored to the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die through a plurality of ridges formed in the second side of the die, the third side of the die, the fourth side of the die, and the fifth side of the die.

16. The package of claim 12 , wherein the plurality of electrical contacts comprise one of a combination of nickel, gold, and aluminum or a combination of tin, silver, and copper.

17. The package of claim 12 , wherein the passivation layer is directly coupled to the mold compound.

18. The package of claim 12 , wherein the interlayer is directly coupled to the mold compound.

19. The package of claim 12 , wherein the package comprises both of the passivation layer and the interlayer coupled between the solder resist layer and the mold compound.

20. The package of claim 12 , further comprising a second mold compound directly coupled to the sixth side of the die.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Kurose Eiji

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/019

  of bond pads · CPC title

• H10W72/01953

  by etching · CPC title