Multi-level memristor elements
US-2021257405-A1 · Aug 19, 2021 · US
Nonlinearity compensation circuit for memristive device
US12340840B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12340840-B2 |
| Application number | US-202217966305-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 14, 2022 |
| Priority date | Nov 30, 2021 |
| Publication date | Jun 24, 2025 |
| Grant date | Jun 24, 2025 |
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- Title
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Abstract
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The present disclosure relates to a nonlinearity compensation circuit for a memristive device. The circuit according to an embodiment includes at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to adjust a pulse width of an update pulse to be applied to the memristive device; and the memristive device to which the modulated update pulse is applied.
First claim
Opening claim text (preview).
What is claimed is: 1. A nonlinearity compensation circuit for a memristive device, comprising: at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to modulate a pulse width of an update pulse applied to the memristive device through the input pulse; and the memristive device to which the modulated update pulse is applied, wherein the modulation unit includes a plurality of first transistors, a plurality of second transistors and a first capacitor. 2. The nonlinearity compensation circuit for a memristive device according to claim 1 , wherein when a conductance of the memristive device includes convex nonlinearity characteristics, the modulation unit modulates the pulse width in inverse proportion to the conductance based on a threshold voltage of the first capacitor. 3. The nonlinearity compensation circuit for a memristive device according to claim 2 , wherein the first capacitor is charged by a current generated in proportion to the conductance using the plurality of first transistors. 4. The nonlinearity compensation circuit for a memristive device according to claim 1 , wherein when a conductance of the memristive device includes concave nonlinearity characteristics, the modulation unit modulates the pulse width in proportion to the conductance based on a threshold voltage of the first capacitor. 5. The nonlinearity compensation circuit for a memristive device according to claim 4 , wherein the first capacitor is charged by a current generated in inverse proportion to the conductance using the plurality of first transistors. 6. The nonlinearity compensation circuit for a memristive device according to claim 1 , wherein the modulation unit turns off the update pulse based on the plurality of second transistors.
Assignees
Inventors
Classifications
- G11C13/0061Primary
Timing circuits or methods · CPC title
- G11C13/0038Primary
Power supply circuits · CPC title
Write characterized by the shape, e.g. form, length, amplitude of the write pulse · CPC title
using elements simulating biological cells, e.g. neuron · CPC title
Writing or programming circuits or methods · CPC title
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- What does patent US12340840B2 cover?
- The present disclosure relates to a nonlinearity compensation circuit for a memristive device. The circuit according to an embodiment includes at least one power source unit to apply an input pulse; a modulation unit connected to the at least one power source unit to adjust a pulse width of an update pulse to be applied to the memristive device; and the memristive device to which the modulated …
- Who is the assignee on this patent?
- Korea Inst Sci & Tech
- What technology area does this patent fall under?
- Primary CPC classification G11C13/0061. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 24 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).