Memory cell and content addressable memory having the same

Patent metadata

Field	Value
Publication number	US-2016284408-A1
Application number	US-201615063345-A
Country	US
Kind code	A1
Filing date	Mar 7, 2016
Priority date	Mar 23, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A memory cell includes a set of storage switch units, a set of memory units, a set of comparison switch units and a discharge switch unit. The storage switch units are turned on by a turn-on signal transmitted by a word line. The memory units receive and store write data transmitted by a bit line or a source line when the storage switch units are on under a write mode. The comparison switch units are turned on by comparison data transmitted by comparison lines under a search mode. The discharge switch unit is turned on by a detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the memory units, so that the reference signal transmitted to the comparator is redirected to a reference voltage. A content addressable memory using the memory cell is also provided.

First claim

What is claimed is:

1 . A memory cell of a content addressable memory, wherein the content addressable memory has a write mode and a search mode, a plurality of the memory cells form a memory array, the memory cell is electrically coupled to a word line, a bit line, a source line and two comparison lines, wherein when the content addressable memory receives a turn-on signal transmitted by the word line under the write mode, the memory cell receives write data transmitted by the bit line or the source line, wherein when the content addressable memory receives the turn-on signal transmitted by the word line under the search mode, the memory cell receives comparison data transmitted by the comparison lines and a detection voltage transmitted by the bit line and transmits a reference signal to a comparator via a match line, wherein whether the comparison data is stored in a memory is determined based on the reference signal received by the compactor, wherein the memory cell comprises:
a set of storage switch units, configured to be turned on by the turn-on signal transmitted by the word line; a set of memory units, configured to receive and store the write data transmitted by the bit line or the source line when the storage switch unit is turned on under the write mode; a set of comparison switch units, configured to be turned on by the comparison data transmitted by the comparison lines under the search mode; and a discharge switch unit, configured to be turned on by the detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the set of memory units, so that the reference signal transmitted by the match line to the comparator is redirected to a reference voltage.

2 . The memory cell according to claim 1 , wherein the set of storage switch units comprise a first transistor and a second transistor, the set of comparison switch units comprise a third transistor and a fourth transistor, the discharge switch unit comprises a fifth transistor, the set of memory units comprise a first memristor and a second memristor, the first transistor and the second transistor of the storage switch units, the third transistor and the fourth transistor of the comparison switch units and the fifth transistor of the discharge switch unit each has a first source/drain, a second source/drain and a gate, the first memristor and the second memristor each has a non-doped terminal and a doped terminal, wherein the gate of the first transistor and the gate of the second transistor are electrically coupled to the word line, the first source/drain of the first transistor is electrically coupled to the first source/drain of the second transistor, the second source/drain of the first transistor is electrically coupled to the non-doped terminal of the first memristor, the doped terminal of the first memristor is electrically coupled to the non-doped terminal of the second memristor, the doped terminal of the second memristor is electrically coupled to the second source/drain of the second transistor, the gate of the third transistor and the gate of the fourth transistor are each electrically coupled to one of the two comparison lines, the first source/drain of the third transistor is electrically coupled between the second source/drain of the first transistor and the non-doped terminal of the first memristor, the second source/drain of the third transistor is electrically coupled to the second source/drain of the fourth transistor, the first source/drain of the fourth transistor is electrically coupled between the second source/drain of the second transistor and the doped terminal of the second memristor, the gate of the fifth transistor is electrically coupled between the second source/drain of the third transistor and the second source/drain of the fourth transistor, the first source/drain of the fifth transistor is electrically coupled to the match line, the second source/drain of the fifth transistor is electrically coupled to the reference voltage, the bit line is electrically coupled to the first source/drain of the first transistor and the first source/drain of the second transistor, the source line is electrically coupled to the doped terminal of the first memristor and the non-doped terminal of the second memristor.

3 . The memory cell according to claim 2 , wherein the memristor has a high resistance state and a low resistance state that are state switchable, wherein when the non-doped terminal of the memristor receives the write data, the memristor is in the low resistance state, wherein when the doped terminal of the memristor receives the write data, the memristor is switched to the high resistance state.

4 . The memory cell according to claim 3 , wherein when the third transistor is turned on by the comparison data and the first memristor is in the high resistance state, the gate of the fifth transistor is driven by the detection voltage and turns on the first source/drain and the second source/drain of the fifth transistor, so that the reference signal is electrically coupled to the reference voltage.

5 . A content addressable memory having a write mode and a search mode, the content addressable memory comprising:
a first current direction selector; a second current direction selector, electrically coupled to the first current direction selector via a plurality of bit lines and a plurality of source lines, wherein a current transmission direction of the bit lines is from the first current direction selector to the second current direction selector and a current transmission direction of the source lines is from the second current direction selector to the first current direction selector, wherein, the bit lines or the source lines transmit write data under the write mode and the bit lines transmit a detection voltage under the search mode; a position decoder, having a plurality of word lines, wherein when the content addressable memory is under the write mode, the position decoder is configured to receive an individual turn-on command, select one of the word lines according to the individual turn-on command, and transmit a turn-on signal via the selected word line, wherein when the content addressable memory is under the search mode, the position decode is configured to receive an all-turn-on command, select all of the word lines according to the all-turn-on command, and transmit the turn-on signal via all of the word lines; a comparator, configured to receive a reference signal transmitted by a plurality of match lines and determine whether comparison data is stored in the memory when receiving the reference signal; and a memory array, comprised of a plurality of memory cells, wherein the memory cell is electrically coupled to one of the word lines, one of the bit lines, one of the source lines and two comparison lines, wherein the memory cell comprises; a set of storage switch units, configured to be turned on by the turn-on signal transmitted by the one of the word lines; a set of memory units, configured to receive and store the write data transmitted by the one of the bit lines or the one of the source lines when the storage switch unit is turned on under the write mode; a set of comparison switch units, configured to be turned on by the comparison data transmitted by the comparison lines under the search mode; and a discharge switch unit, configured to be turned on by the detection voltage under the search mode when the comparison data transmitted by the comparison lines is different from the write data stored in the set of memory units, so that the reference signal transmitted by the match lines to the comparator is transmitted to a reference voltage.

6 . The content addressable memory according to claim 5 , further compri

Assignees

• Univ Nat Cheng Kung

Inventors

• Chiou Lih-Yih
• Chien Tsai-Kan

Classifications

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title

• G11C15/046 Primary

  using non-volatile storage elements · CPC title

• G11C15/04

  using semiconductor elements · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title