Memristor circuit, memristor control system, analog product-sum operator, and neuromorphic device

Patent metadata

Field	Value
Publication number	US-10964369-B2
Application number	US-201916577067-A
Country	US
Kind code	B2
Filing date	Sep 20, 2019
Priority date	Sep 26, 2018
Publication date	Mar 30, 2021
Grant date	Mar 30, 2021

Abstract

A memristor circuit that can increase a maximum rate of change of a conductance of the memristor circuit while maintaining linearity and symmetry in the change in the conductance is provided. A memristor circuit includes: a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit; and a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power supply.

First claim

What is claimed is:

1. A memristor circuit comprising:
a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit;
a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power supply; and
a resistor connected between the power supply and a contact point to which the gate electrode is connected in the transmission path.

2. The memristor circuit according to claim 1 , wherein the resistor has a resistance value which falls within a range between a minimum value and a maximum value of a resistance value of the first resistance change unit.

3. The memristor circuit according to claim 1 ,
wherein the resistor is a second magnetoresistance effect element that includes a second resistance unit of which a magnetization state is fixed, an electrode provided at a first end of the second resistance unit, and an electrode provided at a second end of the second resistance unit,
wherein the electrode provided at the first end of the second resistance unit is connected to the power supply, and
wherein the electrode provided at the second end of the second resistance unit is connected to the contact point.

4. The memristor circuit according to claim 2 ,
wherein the resistor is a second magnetoresistance effect element that includes a second resistance unit configured for a magnetization state thereof to be fixed, an electrode provided at a first end of the second resistance unit, and an electrode provided at a second end of the second resistance unit,
wherein the electrode provided at the first end of the second resistance unit is connected to the power supply, and
wherein the electrode provided at the second end of the second resistance unit is connected to the contact point.

5. The memristor circuit according to claim 1 , wherein the first magnetoresistance effect element is stacked on a substrate by a top pin structure.

6. The memristor circuit according to claim 2 , wherein the first magnetoresistance effect element is stacked on a substrate by a top pin structure.

7. The memristor circuit according to claim 3 , wherein the first magnetoresistance effect element is stacked on a substrate by a top pin structure.

8. The memristor circuit according to claim 1 , wherein the first magnetoresistance effect element is stacked on a substrate by a bottom pin structure.

9. The memristor circuit according to claim 2 , wherein the first magnetoresistance effect element is stacked on a substrate by a bottom pin structure.

10. The memristor circuit according to claim 3 , wherein the first magnetoresistance effect element is stacked on a substrate by a bottom pin structure.

11. A memristor circuit comprising:
a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit; and
a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power,
wherein a switching element is connected between the power supply and the gate electrode.

12. The memristor circuit according to claim 1 , wherein a switching element is connected between the power supply and the gate electrode.

13. The memristor circuit according to claim 2 , wherein a switching element is connected between the power supply and the gate electrode.

14. The memristor circuit according to claim 3 , wherein a switching element is connected between the power supply and the gate electrode.

15. A memristor control system comprising:
a memristor circuit; and
a control unit configured to control the memristor circuit,
wherein the memristor circuit comprises:
a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit; and
a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power supply,

wherein the first magnetoresistance effect element is a domain wall movement magnetoresistance effect element,
wherein the first resistance change unit has a domain wall,
wherein a third electrode is provided at a third end of the first resistance change unit,
wherein, in the first resistance change unit, a resistance value is changed by movement of the domain wall based on a current flowing between the second and third electrodes, and
wherein the control unit changes a resistance value of the first resistance change unit by causing a pulse current with a pulse width to flow based on a resistance value of the first resistance change unit between the second electrode and the third electrode.

16. An analog product-sum operator comprising:
one memristor circuit or a plurality of memristor circuits,
wherein the one memristor circuit or each of the plurality of memristor circuits comprises:
a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit; and
a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power supply.

17. A neuromorphic device comprising:
one memristor circuit or a plurality of memristor circuits,
wherein the one memristor circuit or each of the plurality of memristor circuits comprises:
a first magnetoresistance effect element including a first resistance change unit configured to change a resistance value thereof based on a current flowing therein, a first electrode provided at a first end of the first resistance change unit, and a second electrode provided at a second end of the first resistance change unit; and
a first field effect transistor including a gate electrode, the gate electrode being connected to a transmission path between the first electrode connected to a power supply and the power supply.

Assignees

• Tdk Corp

Inventors

• Shibata Tatsuo

Classifications

• H10N50/85

  Materials of the active region · CPC title

• G11C11/54 Primary

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C11/1697 Primary

  Power supply circuits · CPC title

• G11C11/161

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C11/1659

  Cell access · CPC title