Display panel, method of manufacturing the same and display device

Patent metadata

Field	Value
Publication number	US-12336400-B2
Application number	US-202318107991-A
Country	US
Kind code	B2
Filing date	Feb 9, 2023
Priority date	May 9, 2020
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

The present disclosure provides a display panel and a method of manufacturing the same and a display device. In a sub-pixel driving circuit of the display panel, a gate electrode of a driving transistor is coupled to a second electrode of a second transistor through a fourth conductive connection portion, and a second electrode plate of a storage capacitor is coupled to a second electrode of a first transistor through a third conductive connection portion, a gate electrode of the first transistor and a gate electrode of the second transistor are respectively coupled to a gate line pattern in the corresponding sub-pixel area; orthographic projection of the gate line pattern on the substrate does not overlap orthographic projection of the third conductive connecting portion on the substrate, and/or does not overlap orthographic projection of the fourth conductive connection portion on the substrate.

First claim

What is claimed is:

1. A display panel, comprising: a substrate, a sub-pixel driving circuit film layer arranged on the substrate, a plurality of sub-pixel areas arranged in an array; a power signal line layer, a third auxiliary signal line layer and a first shielding layer, wherein
the third auxiliary signal line layer includes a third auxiliary signal line pattern located in each of the plurality of sub-pixel areas, at least part of the third auxiliary signal line pattern extends along a first direction;
the power signal line layer includes a power signal line pattern located in each of the plurality of sub-pixel areas, at least part of the power signal line pattern extends along a second direction;
the first direction intersects the second direction;
the first shielding layer includes a first shielding pattern located in each of the plurality of sub-pixel areas, at least part of the first shielding pattern extends along the second direction, and the first shielding pattern is coupled to the power signal line pattern;
the sub-pixel driving circuit film layer includes sub-pixel driving circuits corresponding to the plurality of sub-pixel areas in a one-to-one manner, and each sub-pixel driving circuit includes a storage capacitor; and
in a same sub-pixel area, the first shielding pattern and the third auxiliary signal line pattern form an integral structure, the integral structure is arranged in a same layer as a second electrode plate of the storage capacitor, the integral structure is a U-shaped structure, and the storage capacitor is located in the U-shaped structure.

2. The display panel according to claim 1 , wherein the third auxiliary signal line pattern includes a first end and a second end along the first direction, and the first end and the second end are connected to the first shielding pattern, a distance between the first end and the second end connected to the first shielding pattern is greater than a width of the storage capacitor along the first direction.

3. The display panel according to claim 2 , wherein,
a distance between the first end connected to the first shielding pattern and a first electrode plate of the storage capacitor is smaller than a distance between the second end connected to the first shielding pattern and the first electrode plate.

4. The display panel according to claim 3 , further comprising a data line layer, wherein
the data line layer includes a data line pattern located in each of the plurality of sub-pixel areas, at least part of the data line pattern extends along the second direction,
an orthographic projection of the first shielding pattern on the substrate overlaps an orthographic projection of the data line pattern on the substrate.

5. The display panel according to claim 4 , wherein
a width of the orthographic projection of the first shielding pattern on the substrate is greater than a width of the orthographic projection of the data line pattern on the substrate.

6. The display panel according to claim 1 , wherein the sub-pixel driving circuit further comprises a fifth transistor, and the third auxiliary signal line pattern is located between a gate electrode of the fifth transistor and a first electrode plate of the storage capacitor.

7. The display panel according to claim 1 , further comprising a line gate layer and a conductive connection portion layer, wherein
the gate line layer includes a gate line pattern located in each of the plurality of sub-pixel areas, and at least part of the gate line pattern extends along the first direction;
an orthographic projection of a data line pattern on the substrate overlaps orthographic projection of the gate line pattern on the substrate;
the conductive connection portion layer includes a third conductive connection portion and a fourth conductive connection portion located in each of the plurality of sub-pixel areas; and
each of the sub-pixel driving circuits includes: a driving transistor, a first transistor and a second transistor; a gate electrode of the driving transistor is multiplexed as a first electrode plate of the storage capacitor, and the gate electrode of the driving transistor is coupled to a second electrode of the second transistor through the fourth conductive connection portion in a corresponding sub-pixel area, and the second electrode plate of the storage capacitor is coupled to a second electrode of the first transistor through the third conductive connection portion in the corresponding sub-pixel area.

8. The display panel according to claim 7 , wherein in the same sub-pixel area, an orthographic projection of the power signal line pattern on the substrate is located between an orthographic projection of the gate electrode of the driving transistor on the substrate and the orthographic projection of the data line pattern on the substrate.

9. The display panel according to claim 7 , wherein each of an orthographic projection of the third conductive connection portion on the substrate and an orthographic projection of the fourth conductive connection portion on the substrate overlaps an orthographic projection of the storage capacitor on the substrate.

10. The display panel according to claim 9 , wherein a first electrode of the first transistor includes a first electrode portion and a second electrode portion that are coupled to each other, and the first electrode portion extends along the first direction, the second electrode portion extends along the second direction, orthographic projection of the second electrode portion on the substrate overlaps the orthographic projection of a data line pattern in a corresponding sub-pixel area on the substrate, and the second electrode portion is coupled to the data line pattern in the corresponding sub-pixel area through a first connection hole at an overlapping area; orthographic projection of the first connection hole on the substrate and the orthographic projection of a second power supply portion on the substrate are arranged in a direction perpendicular to the second direction.

11. The display panel according to claim 10 , wherein
an orthographic projection of the first electrode portion on the substrate overlaps the orthographic projection of a first power supply portion in the corresponding sub-pixel area on the substrate; and/or,
an orthographic projection of a channel area of the first transistor on the substrate overlaps the orthographic projection of the first power supply portion in the corresponding sub-pixel area on the substrate.

12. The display panel according to claim 6 , further comprising:
an initialization signal line layer, wherein the initialization signal line layer includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas;
an anode layer located on a side of the initialization signal line layer away from the substrate, wherein the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, and the plurality of anode patterns are arranged at intervals, an anode spacing area is formed between adjacent anode patterns; and
a first auxiliary signal line layer, wherein the first auxiliary signal line layer has a grid structure, at least a part of the first auxiliary signal line layer is located in the anode spacing area and is insulated from the anode pattern, the initialization signal line pattern in each of the plurality of sub-pixel areas is coupled to the first auxiliary signal line layer.

13. The display panel according to claim 12 , wherein the conductive connection portion layer further includes a first conductive connection portion arranged in each of the

Assignees

• Boe Technology Group Co Ltd

Inventors

• Chen Yipeng
• Huangfu Lujiang
• Liu Libin

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title