Display substrate including shielding pattern overlapping reset transistor, method for manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-12225784-B2
Application number	US-202017418136-A
Country	US
Kind code	B2
Filing date	Aug 31, 2020
Priority date	Aug 31, 2020
Publication date	Feb 11, 2025
Grant date	Feb 11, 2025

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. In the display substrate, the sub-pixel driving circuit includes a driving transistor and a first reset transistor, and a gate electrode of the first reset transistor is electrically connected to the reset signal line pattern, a first electrode of the first reset transistor is electrically connected to the initialization signal line pattern, and a second electrode of the first reset transistor is electrically connected to a gate electrode of the driving transistor; and the shielding pattern is electrically connected to the power signal line pattern, an orthographic projection of the shielding pattern on the substrate overlaps an orthographic projection of the first electrode of the first reset transistor on the substrate.

First claim

What is claimed is:

1. A display substrate, comprising: a substrate and a plurality of sub-pixels arranged in an array on the substrate, wherein the plurality of sub-pixels includes:
an initialization signal line pattern, at least part of the initialization signal line pattern extending along a first direction;
a reset signal line pattern, at least part of the reset signal line pattern extending along the first direction;
a power signal line pattern, at least a part of the power signal line pattern extending along a second direction, the second direction intersecting the first direction;
a sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a driving transistor and a first reset transistor, and a gate electrode of the first reset transistor is electrically connected to the reset signal line pattern, a first electrode of the first reset transistor is electrically connected to the initialization signal line pattern, and a second electrode of the first reset transistor is electrically connected to a gate electrode of the driving transistor; and
a shielding pattern, wherein the shielding pattern is electrically connected to the power signal line pattern, an orthographic projection of the shielding pattern on the pixel unit, and the shielding pattern is electrically connected to the power signal line pattern through a connection hole;
wherein the second electrode of the first reset transistor is electrically connected to the gate electrode of the driving transistor through a fifth conductive connection portion, an orthographic projection of the connection hole on the substrate is located between an orthographic projection of the gate electrode of the first reset transistor on the substrate and an orthographic projection of the fifth conductive connection portion on the substrate in plan view.

2. The display substrate according to claim 1 , wherein the orthographic projection of the shielding pattern on the substrate does not overlap an orthographic projection of the reset signal line pattern on the substrate.

3. The display substrate according to claim 1 , wherein the orthographic projection of the shielding pattern on the substrate overlaps an orthographic projection of the second electrode of the first reset transistor on the substrate.

4. The display substrate according to claim 1 , wherein the plurality of sub-pixels includes:
a first sub-pixel and a second sub-pixel arranged along the second direction, wherein the first sub-pixel includes a first data line pattern, and the second sub-pixel includes a second data line pattern, at least part of the first data line pattern and at least part of the second data line pattern extend along the second direction, and the first data line pattern is located on a first side of a same column of first sub-pixels extending along the second direction, the second data line pattern is located on a second side of a same column of second sub-pixels extending along the second direction, the first side is opposite to the second side along the first direction, and the first direction intersects the second direction; and
a third sub-pixel and a fourth sub-pixel arranged along the second direction, wherein along the first direction, the third sub-pixel and the first sub-pixel are located in a same row, the fourth sub-pixel and the second sub-pixel are located in a same row; the third sub-pixel includes a third data line pattern, the fourth sub-pixel includes a fourth data line pattern, and at least part of the third data line pattern and at least part of the fourth data line pattern extend along the second direction, and the third data line pattern is located on a second side of a same column of third sub-pixels extending along the second direction, the fourth data line pattern is located on a first side of a same column of fourth sub-pixels extending along the second direction;
wherein in the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the power signal line patterns includes: a power main body and a power protruding portion that are electrically connected;
in the first sub-pixel, an orthographic projection of the power protruding portion on the substrate overlaps the orthographic projection of the first data line pattern on the substrate, and an orthographic projection of the power main portion on the substrate at least partially overlaps an orthographic projection of an adjacent data line pattern along the first direction on the substrate;
wherein the adjacent data line pattern along the first direction is the third data line pattern;
wherein the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include:
a power compensation pattern, at least part of the power compensation pattern extends along the first direction, the power signal line pattern and the power compensation pattern are both located at a side of the first data line pattern, the second data line pattern, the third data line pattern, and the fourth data line pattern close to the substrate;
the power compensation pattern is electrically connected to a power signal line pattern in a sub-pixel to which the power compensation pattern belongs and a power signal line pattern in an adjacent sub-pixel along the first direction;
wherein a first end of the power compensation pattern is electrically connected to a power protruding portion of a sub-pixel to which the power compensation pattern belongs; a second end of the power compensation pattern is electrically connected to a power main body of an adjacent sub-pixel along the first direction;
wherein there is a gap between the power protruding portion and the power main body.

5. The display substrate according to claim 4 , wherein
the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel each include a first conductive connection portion and a fifth conductive connection portion;
in the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel,
the sub-pixel driving circuit includes a data writing transistor;
the first conductive connection portion is respectively electrically connected to a corresponding data line pattern and a first electrode of the data writing transistor, a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;
the second electrode of the first reset transistor is electrically connected to the gate electrode of the driving transistor through the fifth conductive connection portion;
the orthographic projection of the shielding pattern on the substrate at least partially overlaps the orthographic projection of the first conductive connection portion on the substrate.

6. The display substrate according to claim 5 , wherein the orthographic projection of at least part of the shielding pattern on the substrate is located between the orthographic projection of the first conductive connection portion on the substrate and an orthographic projection of the fifth conductive connection portion on the substrate.

7. The display substrate according to claim 4 , wherein in the first sub- pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel, the sub-pixel driving circuit includes a first transistor, a first electrode of the first transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the first transistor is electrically connected to the gate electrode of the driving transistor;
an active pattern of the first transistor includes two semiconductor portions arranged at intervals, and a first conductor portion respectively connected to the two semiconductor portions;
the projection of the shielding pattern on the substrate at

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Shang Tinghua
• Zhang Yi
• Liu Tingliang
• Han Linhong
• Yang Huijuan
• Zhang Shun
• Wang Yu

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title