Display panel, method of manufacturing the same and display device

Patent metadata

Field	Value
Publication number	US-11903289-B2
Application number	US-202217948576-A
Country	US
Kind code	B2
Filing date	Sep 20, 2022
Priority date	May 9, 2020
Publication date	Feb 13, 2024
Grant date	Feb 13, 2024

Abstract

A display panel, a method of manufacturing the same, and a display device are provided. In the display panel, sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each sub-pixel area group includes at least two adjacent sub-pixel areas, a connection layer includes a connection pattern arranged in each sub-pixel area, and the connection pattern is coupled to the initialization signal line pattern in the sub-pixel area wherein the connection pattern is located, connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion; at least part of a first auxiliary signal line layer is located in an anode spacing area, and is insulated from an anode pattern, the connection pattern in each sub-pixel area group is coupled to the first auxiliary signal line layer.

First claim

What is claimed is:

1. A display panel, comprising: a substrate, a first shielding layer, a plurality of sub-pixel areas arranged in an array, and a plurality of sub-pixel driving circuits corresponding to the plurality of sub-pixel areas in a one-to-one manner, wherein
each of the plurality of sub-pixel driving circuits includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, and the first electrode plate is located between the substrate and the second electrode plate,
the first shielding layer includes a first shielding pattern located in each of the plurality of sub-pixel areas, the first shielding pattern and the second electrode plate are arranged at a same layer, and the first shielding pattern is located between two adjacent second electrode plates of two adjacent sub-pixel areas,
the first shielding pattern and the second electrode plate are alternately arranged along a first direction, a projection of the first shielding pattern on a line extending along the first direction does not overlap a projection of the second electrode plate on the line extending along the first direction, and a projection of the first shielding pattern on a line extending along a second direction overlaps a projection of the second electrode plate on the line extending along the second direction, and the first direction intersects the second direction.

2. The display panel according to claim 1 , wherein a distance in the first direction between at least one of the first shielding patterns and one of the two adjacent second electrode plates is different from a distance in the first direction between the at least one of the first shielding patterns and the other of the two adjacent second electrode plates.

3. The display panel according to claim 1 , further comprising:
a data line layer, wherein the data line layer includes a data line pattern located in each of the sub-pixel areas, at least part of the data line pattern extends along the second direction; and
a power supply signal line layer, wherein the power supply signal line layer includes a power supply signal line pattern located in each of the sub-pixel regions, and at least part of the power supply signal line pattern extends along the second direction.

4. The display panel according to claim 3 , wherein
the power signal line pattern includes a first power supply portion and a second power supply portion coupled to each other, and the first power supply part extends along the second direction; a width of the first power supply portion is greater than a width of the second power supply portion in a direction perpendicular to the second direction and parallel to the substrate.

5. The display panel according to claim 4 , wherein,
a potential of the first shielding pattern is a potential provided by the first power supply portion.

6. The display panel according to claim 5 , wherein an orthographic projection of the first shielding pattern on the substrate overlaps an orthographic projection of the first power supply portion on the substrate, the first shield pattern is coupled to the first power supply portion at the overlapping area.

7. The display panel according to claim 6 , wherein,
an orthographic projection of the first electrode of the driving transistor on the substrate overlaps an orthographic projection of a first power supply portion in a corresponding sub-pixel area on the substrate, and the first electrode of the driving transistor is coupled to the first power supply portion at the overlapping area.

8. The display panel according to claim 3 , wherein,
a length of the first shielding pattern in the second direction is greater than a length of the second electrode plate in the second direction.

9. The display panel according to claim 5 , further comprising a third auxiliary signal line layer, wherein the third auxiliary signal line layer includes a third auxiliary signal line pattern of a wavy structure in each of the plurality of sub-pixel areas, a potential of the third auxiliary signal line is a potential provided by the first power supply portion.

10. The display panel according to claim 3 , wherein, in a same sub-pixel area, the orthographic projection of the power signal line pattern on the substrate is located between an orthographic projection of the gate electrode of the driving transistor on the substrate and an orthographic projection of the data line pattern on the substrate.

11. The display panel according to claim 3 , wherein at least part of the first shielding pattern extends along the second direction, and an orthographic projection of the first shielding pattern on the substrate overlaps an orthographic projections of the data line pattern on the substrate.

12. The display panel according to claim 3 , further comprising
a conductive connection portion layer, wherein the conductive connection portion layer includes a third conductive connection portion located in each of the plurality of sub-pixel areas;
each of the sub-pixel driving circuits further includes a first transistor for controlling the writing of the data signal, and the second electrode plate of the storage capacitor is coupled to a second electrode of the first transistor through the third conductive connection portion in the corresponding sub-pixel area.

13. The display panel according to claim 1 , wherein sub-pixel areas in a same row along a first direction are divided into a plurality of sub-pixel area groups independent from each other, and each of the plurality of sub-pixel area groups includes at least two adjacent sub-pixel areas; the display panel further includes: an initialization signal line layer, a connection layer and an anode layer that are sequentially stacked on the substrate along a direction away from the substrate;
the initialization signal line layer includes an initialization signal line pattern arranged in each of the plurality of sub-pixel areas;
the connection layer includes a connection pattern arranged in each of the plurality of sub-pixel areas, at least part of the connection pattern extends along the first direction, and the connection pattern is coupled to the initialization signal line pattern in a sub-pixel area where the connection pattern is located; connection patterns located in a same sub-pixel area group are sequentially coupled along the first direction to form the connection portion;
the anode layer includes a plurality of anode patterns corresponding to the plurality of sub-pixel areas in a one-to-one manner, the plurality of anode patterns are arranged at intervals, and an anode spacing area is formed between adjacent anode patterns;
the display panel further includes: a first auxiliary signal line layer, the first auxiliary signal line layer is a grid structure, and at least part of the first auxiliary signal line layer is located in the anode spacing area, and is insulated from the anode pattern, the connection pattern in each of the plurality of sub-pixel area groups is coupled to the first auxiliary signal line layer.

14. The display panel according to claim 13 , wherein:
the conductive connection layer includes a first conductive connection portion located in each of the plurality of sub-pixel areas, and in a same sub-pixel area, a first overlapping area is formed between an orthographic projection of the first conductive connection portion on the substrate and an orthographic projection of the initialization signal line pattern on the substrate, and the first conductive connection portion is coupled to the initialization signal line patt

Assignees

• Boe Technology Group Co Ltd

Inventors

• Chen Yipeng
• Huangfu Lujiang
• Liu Libin

Classifications

• H10K59/353 Primary

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/352

  the areas of the RGB subpixels being different · CPC title