Stacked image sensors

Patent metadata

Field	Value
Publication number	US-12336315-B2
Application number	US-202318482923-A
Country	US
Kind code	B2
Filing date	Oct 9, 2023
Priority date	Oct 28, 2022
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

The stacked image sensor includes a first semiconductor substrate and including a photoelectric conversion region and a floating diffusion area, a first insulating layer under the first semiconductor substrate and including a gate of a transfer transistor, a second semiconductor substrate under the first insulating layer and including first impurities of a first conductivity type, and a second insulating layer under the second semiconductor substrate and including a metal pad of a floating diffusion node and a gate of a source follower transistor, wherein the floating diffusion area and the metal pad of the floating diffusion node are electrically connected through a deep contact that is in the first insulating layer and the second semiconductor substrate. The second semiconductor substrate further includes a well region. At least a portion of deep contact may be in the well region. The well region may surround the deep contact.

First claim

What is claimed is:

1. A stacked image sensor comprising:
a first semiconductor substrate including a photoelectric conversion region and a floating diffusion area configured to store charges transferred from the photoelectric conversion region;
a color filter and a micro lens on the first semiconductor substrate;
a first insulating layer under the first semiconductor substrate;
a transfer transistor configured to transfer charges from the photoelectric conversion region, wherein a gate of the transfer transistor is in the first insulating layer;
a second semiconductor substrate under the first insulating layer and including first impurities of a first conductivity type, wherein the second semiconductor substrate includes a well region;
a second insulating layer under the second semiconductor substrate;
a metal pad of a floating diffusion node and a gate of a source follower transistor in the second insulating layer; and
a deep contact that is in the first insulating layer and the second semiconductor substrate and electrically connects the floating diffusion area to the metal pad of the floating diffusion node,
wherein at least a portion of the deep contact is in the well region.

2. The stacked image sensor of claim 1 , wherein the well region includes second impurities of a second conductivity type.

3. The stacked image sensor of claim 2 , wherein the second conductivity type is an N-type.

4. The stacked image sensor of claim 1 , wherein the well region is electrically connected to a source region of the source follower transistor, and the gate of the source follower transistor is electrically connected to the floating diffusion node.

5. The stacked image sensor of claim 4 , wherein the well region and the source region of the source follower transistor are spaced apart from each other in a horizontal direction, and
the stacked image sensor further comprising:
a first vertical contact connected to the well region;
a second vertical contact connected to the source region of the source follower transistor; and
a metal pad connecting the first vertical contact and the second vertical contact to each other.

6. The stacked image sensor of claim 1 , wherein the well region includes a conductive material.

7. A stacked image sensor comprising:
a first semiconductor chip including a two-dimensionally arranged plurality of pixels in an upper region of the first semiconductor chip and a first insulating layer in a lower region of the first semiconductor chip;
a second semiconductor chip including at least one transistor configured to output a pixel signal of the plurality of pixels and a second insulating layer in a lower region of the second semiconductor chip, wherein the second semiconductor chip includes a well region that includes first impurities and is electrically connected to a source region of the at least one transistor; and
a third semiconductor chip including a circuit configured to process the pixel signal,
wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through a deep contact extending in a vertical direction, and
wherein at least a portion of the deep contact is in the well region.

8. The stacked image sensor of claim 7 , wherein the second semiconductor chip further comprises a second substrate including second impurities, and the well region is in the second substrate, and
wherein the well region and the second substrate have an equal thickness in the vertical direction.

9. The stacked image sensor of claim 7 , wherein the well region is electrically connected to a source region of a source follower transistor.

10. The stacked image sensor of claim 8 , wherein the first impurities are N-type impurities, and the second impurities are P-type impurities.

11. A stacked image sensor comprising:
a pixel array including a plurality of pixels;
a row driver configured to transmit a boosting signal to the pixel array; and
a readout circuit configured to read out pixel signals output from the plurality of pixels of a row selected by the row driver,
wherein each of the plurality of pixels comprises:
a photodiode;
a transfer transistor electrically connected to the photodiode;
a floating diffusion node configured to store charges generated by the photodiode;
a deep contact capacitor connected to an output terminal of the transfer transistor; and
a source follower transistor including one end electrically connected to a pixel voltage, a gate electrically connected to the floating diffusion node, and a source electrically connected to the deep contact capacitor.

12. The stacked image sensor of claim 11 , wherein the transfer transistor is in a first area of the stacked image sensor,
wherein the source follower transistor is in a second area of the stacked image sensor, and
wherein the first area is above the second area.

13. The stacked image sensor of claim 12 , wherein a floating diffusion area configured to store charges from the photodiode is in the first area, and a metal pad of the floating diffusion node electrically connected to the floating diffusion area is in the second area.

14. The stacked image sensor of claim 13 , wherein the first and second areas are stacked in a vertical direction, and
wherein the deep contact capacitor is a capacitor including a deep contact area that extends in the vertical direction and electrically connects the floating diffusion area to the metal pad of the floating diffusion node.

15. The stacked image sensor of claim 14 , wherein the deep contact area comprises:
a deep contact extends in the second area in the vertical direction; and
a well region, wherein at least a portion of the deep contact is in the well region.

16. The stacked image sensor of claim 15 , wherein a source of the source follower transistor is electrically connected to the well region.

17. The stacked image sensor of claim 16 , wherein the well region includes first impurities different from second impurities included in the second area.

18. The stacked image sensor of claim 16 , wherein the well region includes N-type impurities, and the second area includes P-type impurities.

19. The stacked image sensor of claim 16 , wherein the well region includes a conductive material, and the second area including a region that includes P-type impurities.

20. The stacked image sensor of claim 19 , wherein the well region and the region of the second area have an equal thickness in the vertical direction.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Dongseok
• Park Jongeun
• Kang Jeongsoon
• Park Gyunha
• Lee Gwideok Ryan

Classifications

• H10F39/182

  Colour image sensors · CPC title

• H04N25/77

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/78

  Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title