Array of vertical transistors and method used in forming an array of vertical transistors

Patent metadata

Field	Value
Publication number	US-12336288-B2
Application number	US-202217947401-A
Country	US
Kind code	B2
Filing date	Sep 19, 2022
Priority date	Jul 21, 2020
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

First claim

The invention claimed is:

1. A method used in forming an array of vertical transistors, comprising:
forming laterally-spaced and horizontally-elongated line constructions in a column direction; the line constructions comprising insulator material, metal material above the insulator material, transistor material above the metal material, and insulating material on lateral sides of the insulator material, the metal material, and the transistor material; the transistor material comprising an upper source/drain region above a channel region of what will be individual vertical transistors, the insulator material of the line constructions being above conductive material;
forming a horizontally-elongated conductive line in the column direction between immediately-laterally-adjacent of the line constructions and directly against the conductive material, the conductive lines individually comprising a top surface that is higher than a top surface of the metal material and at or below a bottom of the channel region;
after forming the conductive lines, etching the transistor material to form spaced pillars individually comprising the upper source/drain region and the channel region of the individual vertical transistors; and
forming a horizontally-elongated conductive gate line operatively aside the channel region of individual of the pillars that interconnects a respective plurality of the vertical transistors in a row direction.

2. The method of claim 1 wherein the conductive lines are individually formed to be self-aligned in the row direction.

3. The method of claim 1 wherein the conductive lines remain in a finished construction of the array.

4. The method of claim 1 comprising etching the conductive lines so they do not remain in a finished construction of the array.

5. The method of claim 1 comprising etching the conductive lines to form spaced conductive pillars projecting upwardly from the conductive material.

6. The method of claim 1 comprising etching the conductive lines to form spaced conductive pillars projecting upwardly from conducting material of conductive lines.

7. The method of claim 1 comprising forming the upper source/drain region of the transistor material to comprise conductor oxide material.

8. The method of claim 7 wherein the conductor oxide material of the upper source/drain region comprises a first conductor oxide material above and directly against a second conductor oxide material, the first and second conductor oxide materials comprising different compositions relative one another.

9. The method of claim 1 comprising forming the transistor material to comprise a lower source/drain region below the channel region, the lower source/drain region comprising first conductive oxide material.

10. The method of claim 9 wherein the transistor material of the lower source/drain region comprises a second conductive oxide material below and directly against the first conductive oxide material, the first and second conductive oxide materials comprising different compositions relative one another.

11. The method of claim 1 wherein the first and second conductive oxide materials comprise indium tin oxide.

12. The method of claim 1 wherein the first and second conductive oxide materials comprise indium oxide.

13. The method of claim 1 wherein the first and second conductive oxide materials comprise tin oxide.

14. The method of claim 1 wherein the first and second conductive oxide materials comprise zinc oxide.

15. The method of claim 1 wherein the first and second conductive oxide materials comprise titanium oxide.

16. The method of claim 1 wherein the first and second conductive oxide materials comprise ruthenium oxide.

17. The method of claim 1 wherein the channel region comprises an oxide semiconductor material.

18. The method of claim 17 wherein the oxide semiconductor material comprises one or more of Zn x Sn y O, In x Zn y O, Zn x O, In x Ga y Zn z O, In x Ga y Si z O a , In x W y O, In x O, Sn x O, Ti x O, Zn x ON z , Mg x Zn y O, Zr x In y Zn z O, Hf x In y Zn z O, Sn x In y Zn z O, Al x Sn y In z Zn a O, Si x In y Zn z O, Al x Zn y Sn z O, Ga x Zn y Sn z O, Zr x Zn y Sn z O, and In x Ga y Si z O.

19. The method of claim 1 wherein the vertical transistors comprise individual memory cells of a memory array.

Assignees

• Micron Technology Inc

Inventors

• Lee Yi Fang
• Guha Jaydip
• Heineck Lars P
• Karda Kamal M
• Lee Si-Woo
• Mcdaniel Terrence B
• Sills Scott E
• Torek Kevin J
• Yang Sheng-Wei

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/80

  characterised by multiple passive components, e.g. resistors, capacitors or inductors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title