High performance constant cache and constant access mechanisms

Patent metadata

Field	Value
Publication number	US-12333306-B2
Application number	US-202117213874-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Mar 26, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A graphics processing apparatus includes a graphics processor and a constant cache. The graphics processor has a number of execution instances that will generate requests for constant data from the constant cache. The constant cache stores constants of multiple constant types. The constant cache has a single level of hierarchy to store the constant data. The constant cache has a banking structure based on the number of execution instances, where the execution instances generate requests for the constant data with unified messaging that is the same for the different types of constant data.

First claim

What is claimed is:

1. A graphics processing apparatus comprising:
a graphics processor including a number of execution instances to generate requests for constant data; and
a constant cache to store multiple constant types including bindless, stateless constants not bound to a specific storage location and not having a specific state defined, wherein the constant cache has a single level of hierarchy to store the constant data, wherein the constant cache has a banking structure based on the number of execution instances, and wherein the execution instances are to generate requests for the constant data with unified messaging having a single type of data referencing for the multiple constant types.

2. The graphics processing apparatus of claim 1 , wherein the constant cache comprises a cache device off the graphics processor and shared among the execution instances.

3. The graphics processing apparatus of claim 1 , wherein the number of execution instances comprises a number of hardware execution units, and where the constant cache has a banking structure based on the number of hardware execution units.

4. The graphics processing apparatus of claim 1 , wherein the number of execution instances comprises a number of threads executed by a graphics program, and wherein the constant cache has a banking structure based on the number of threads.

5. The graphics processing apparatus of claim 1 , further comprising:
a cacheability manager, at compile-time of a graphics application, to identify constants to store in the constant cache and identify constants to not store in the constant cache.

6. The graphics processing apparatus of claim 5 , wherein the graphics application comprises a shader application.

7. The graphics processing apparatus of claim 5 , wherein the cacheability manager is to iteratively cause compilation of the graphics application with selected constants to store in the constant cache and selected constants to not store in the constant cache, determine a performance of the graphics application, and change which constants are selected to store in the constant cache and which constants are selected to not store in the constant cache based on improved performance of the graphics application.

8. A computer system comprising:
a graphics processing unit including
a graphics processor having a number of execution instances to generate requests for constant data; and
a constant cache to store multiple constant types including bindless, stateless constants not bound to a specific storage location and not having a specific state defined, wherein the constant cache has a single level of hierarchy to store the constant data, wherein the constant cache has a banking structure based on the number of execution instances, and wherein the execution instances are to generate requests for the constant data with unified messaging having a single type of data referencing for the multiple constant types; and

a central processing unit to execute a graphics driver including a compiler to compile a graphics application for execution on the graphics processing unit.

9. The computer system of claim 8 , wherein the constant cache comprises a cache device off the graphics processor and shared among the execution instances.

10. The computer system of claim 8 , wherein the number of execution instances comprises a number of hardware execution units, and where the constant cache has a banking structure based on the number of hardware execution units.

11. The computer system of claim 8 , wherein the number of execution instances comprises a number of threads executed by a graphics program, and wherein the constant cache has a banking structure based on the number of threads.

12. The computer system of claim 8 , wherein the central processing unit is to execute a cacheability manager which, at compile-time of a graphics application, is to identify constants to store in the constant cache and identify constants to not store in the constant cache.

13. The computer system of claim 12 , wherein the graphics application comprises a shader application.

14. The computer system of claim 12 , wherein the cacheability manager is to iteratively cause compilation of the graphics application with selected constants to store in the constant cache and selected constants to not store in the constant cache, determine a performance of the graphics application, and change which constants are selected to store in the constant cache and which constants are selected to not store in the constant cache based on improved performance of the graphics application.

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam
• Shetty Sudarshanram
• Schluessler Travis
• Lueh Guei-Yuan
• Cheung Pinghang
• Karumuri Srividya
• Gurram Chandra S
• Mu shuai
• Vemulapalli Vikranth

Classifications

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3009

  Thread control instructions · CPC title

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F12/0837

  with software control, e.g. non-cacheable data · CPC title