Independent and separate entity-based cache

Patent metadata

Field	Value
Publication number	US-2018293170-A1
Application number	US-201715483001-A
Country	US
Kind code	A1
Filing date	Apr 10, 2017
Priority date	Apr 10, 2017
Publication date	Oct 11, 2018
Grant date	—

Abstract

A mechanism is described for facilitating independent and separate entity-based graphics cache at computing devices. A method of embodiments, as described herein, includes facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

First claim

What is claimed is:

1 . An apparatus comprising:
mapping/implementing logic, as facilitated by or at least partially implemented in a processor, to facilitate hosting of a plurality of cache at a plurality of entities associated with the processor including a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

2 . The apparatus of claim 1 , wherein the mapping/implementation logic is further to map each of the plurality of cache to a system cache or memory, wherein each cache having a direct path to a data port associated with the memory.

3 . The apparatus of claim 2 , wherein the direct path is established without having to employ an internal fabric.

4 . The apparatus of claim 1 , wherein each of the plurality of cache comprises a graphics cache, wherein each cache of the plurality of cache is independent of and separate from other cache of the plurality of cache.

5 . The apparatus of claim 1 , further comprising scalability/coherency logic, as facilitated by or at least partially implemented in a processor, to support coherency between the plurality of entities without the use of the internal fabric, wherein the coherency is supported when performing one or more tasks including one or more compute tasks.

6 . The apparatus of claim 5 , wherein the scalability/coherency logic is further to support pixel hashing across the plurality of entities without having to employ an inter-entity cacheline sharing for workloads including three-dimensional (3D) workloads.

7 . The apparatus of claim 6 , wherein the graphics processor is co-located with the application processor on a common semiconductor package.

8 . A method comprising:
facilitate hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

9 . The method of claim 8 , further comprising mapping each of the plurality of cache to a system cache or memory, wherein each cache having a direct path to a data port associated with the memory.

10 . The method of claim 9 , wherein the direct path is established without having to employ an internal fabric.

11 . The method of claim 8 , wherein each of the plurality of cache comprises a graphics cache, wherein each cache of the plurality of cache is independent of and separate from other cache of the plurality of cache.

12 . The method of claim 8 , further comprising supporting coherency between the plurality of entities without the use of the internal fabric, wherein the coherency is supported when performing one or more tasks including one or more compute tasks.

13 . The method of claim 12 , further comprising supporting pixel hashing across the plurality of entities without having to employ an inter-entity cacheline sharing for workloads including three-dimensional (3D) workloads.

14 . The method of claim 8 , wherein the graphics processor is co-located with the application processor on a common semiconductor package.

15 . At least one machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
facilitating hosting of a plurality of cache at a plurality of entities associated with a graphics processor, wherein each entity hosts at least one cache, and wherein an entity includes a dual sub-slice (DSS) or a streaming multiprocessor (SM).

16 . The machine-readable medium of claim 15 , wherein the operations further comprise mapping each of the plurality of cache to a system cache or memory, wherein each cache having a direct path to a data port associated with the memory.

17 . The machine-readable medium of claim 16 , wherein the direct path is established without having to employ an internal fabric.

18 . The machine-readable medium of claim 15 , wherein each of the plurality of cache comprises a graphics cache, wherein each cache of the plurality of cache is independent of and separate from other cache of the plurality of cache.

19 . The machine-readable medium of claim 15 , wherein the operations further comprise supporting coherency between the plurality of entities without the use of the internal fabric, wherein the coherency is supported when performing one or more tasks including one or more compute tasks.

20 . The machine-readable medium of claim 19 , wherein the operations further comprise supporting pixel hashing across the plurality of entities without having to employ an inter-entity cacheline sharing for workloads including three-dimensional (3D) workloads, wherein the graphics processor is co-located with the application processor on a common semiconductor package.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Ray Joydeep
• Valerio James A
• Appu Abhishek R
• Ranganathan Vasanth

Classifications

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/0875

  with dedicated cache, e.g. instruction or stack · CPC title

• G06T1/60

  Memory management · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title