Apparatus with calibration input mechanism and methods for operating the same

Patent metadata

Field	Value
Publication number	US-12333191-B2
Application number	US-202318513438-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Jan 17, 2023
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Methods, apparatuses, and systems related to calibrating memory circuitry according to externally provided reference voltage are described. A memory device may include a calibration control logic that at least isolates an internal reference voltage from an internal buffer. The internal buffer may receive and process the externally provided reference voltage instead of command-address signals for calibration purposes.

First claim

We claim:

1. A calibration system, comprising:
a tester configured to provide an external reference voltage for a command-address (CA) input buffer (IB) calibration process;
an input connector couplable to the tester and configured to convey at least the external reference voltage; and
a target memory device couplable to the tester through the input connector, the target memory device including:
a CA pad configured to receive (1) commands and addresses from a memory controller for memory operations during normal operation and (2) connect to the set of input connectors and receive the external reference voltage during the CA IB calibration process;
an IB connected to the CA pad and configured to identify the commands and the addresses during the normal operation according to a trim setting and an internal reference voltage, wherein the CA IB calibration process is for determining the trim setting for the IB; and
a calibration control logic coupled to the CA pad and the IB, the calibration control logic configured to (1) provide the external reference voltage to the IB and (2) isolate the IB from the internal reference voltage during the CA IB calibration process.

2. The system of claim 1 , wherein:
the tester is configured to provide the external reference voltage and manage the CA IB calibration process simultaneously for two or more devices-under-test (DUTs) including the target memory device; and
the input connector connects the tester in parallel to the two or more DUTs.

3. The system of claim 2 , wherein:
each of the two or more DUTs include a plurality of CA pads, wherein each CA pad is connected to a corresponding IB; and
the tester is configured to provide the external reference voltage and manage the CA IB calibration process simultaneously for the plurality of CA pads and the corresponding IBs.

4. The system of claim 1 , wherein:
the CA IB calibration process includes at least a first transition and a second transition that change a controlling device between the tester and the target memory device;
the tester is configured to use (1) an asynchronous signal and (2) a bidirectional signal to control to coordinate the first and second transitions.

5. The system of claim 1 , wherein:
the asynchronous signal is an error reporting signal provided by the target memory device;
the bidirectional signal is a test data (TDQ) signal;
the tester is configured to initiate the CA IB calibration process by setting a mode control signal, wherein the TDQ signal is controlled by the target memory device at the initiation of the CA IB calibration process;
the first transition is initiated by a transition in the error reporting signal after the initiation of the CA IB calibration process,
wherein the TDQ signal is controlled by the tester after the first transition, and
wherein the tester provides the external reference voltage while controlling the TDQ signal;

the second transition is initiated by the tester adjusting the TDQ signal after the first transition,
wherein the TDQ signal is controlled by the target memory device after the second transition, and
wherein the target memory device (1) captures a CA state based on the external reference voltage provided to the IB according to the adjustment of the TDQ signal and (2) subsequently provides results associated with the captured CA state to the tester for determining the trim setting for the IB.

6. A memory device, comprising:
a command-address (CA) pad configured to receive (1) a CA signal for memory operations during normal operation and (2) an external reference voltage during a CA input buffer (IB) calibration process;
an IB connected to the CA pad and configured to identify the commands and the addresses during the normal operation according to a trim setting and an internal reference voltage, wherein the CA IB calibration process is for determining the trim setting for the IB;
a calibration control logic coupled to the CA pad and the IB, the calibration control logic configured to (1) provide the external reference voltage to the IB and (2) isolate the IB from the internal reference voltage during the CA IB calibration process; and
an IB calibration circuit coupled to the IB and configured to implement the CA IB calibration process at the memory device using the external reference voltage.

7. The memory device of claim 6 , wherein:
the calibration control logic is configured to receive a mode control signal for initiating the CA IB calibration process; and
the calibration control logic includes an internal-isolation switch coupled between the IB and the internal reference voltage, the internal-isolation switch configured to isolate the IB from the internal reference voltage according to activation of the mode control signal.

8. The memory device of claim 7 , wherein:
the IB includes differential inputs, wherein a first differential input is coupled to the CA pad and a second differential input is coupled to the internal reference voltage through the internal-isolation switch; and
the calibration control logic includes a differential-connection switch connected across the first and second differential inputs and configured to operate complementarily with the internal-isolation switch for connecting both the first and second differential inputs to the external reference voltage according to activation of the mode control signal.

9. The memory device of claim 6 , wherein:
the CA pad comprises a plurality of CA pads that each correspond to an IB; and
the IB calibration circuit is configured to calibrate all IBs on the memory device simultaneously using the external reference voltage.

10. The memory device of claim 9 , wherein the IB calibration circuit is configured to:
generate a set of calibration results;
capture the set of calibration results in parallel;
convert the captured calibration results from parallel to a serial sequence using an output formatting circuit; and
provide the captured set of calibration results in serial format using a bidirectional communication connection to a tester.

11. The memory device of claim 7 , wherein the IB calibration circuit is configured to initiate local operations of the CA IB calibration process in response to the mode control signal, wherein the local operations of the CA IB calibration process includes (1) transitioning an asynchronous signal for coordinating a control transfer to a tester and (2) suspending a clock signal.

12. The memory device of claim 11 , wherein:
the IB calibration circuit is configured to receive a test data signal controlled by the tester following the transition of the asynchronous signal; and
the IB calibration circuit is configured to receive the external reference voltage following the transition of the asynchronous signal.

13. The memory device of claim 12 , wherein the IB calibration circuit is configured to:
identify a subsequent transition in the test data signal as implemented by the tester;
in response to the subsequent transition, capture a result according to the external reference voltage processed by the IB;
reestablish control over the test data signal following the subsequent transition; and
restore CA operations for the IB instead of receiving the external reference voltage.

14. A method of calibrating an internal buffer (IB) configured to process command-address (CA) signals during normal operations for a memory device, the method comprising:
receiving an external reference voltage from a tester during a CA IB calibration process;
providing the external reference voltage to the IB while isolating the IB from an internal reference voltage du

Assignees

• Micron Technology Inc

Inventors

• Werhane Kevin G
• Vankayala Vijayakrishna J
• Jensen Tyrel Z

Classifications

• G06F3/0604 Primary

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title