Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

Patent metadata

Field	Value
Publication number	US-10089256-B2
Application number	US-201715616785-A
Country	US
Kind code	B2
Filing date	Jun 7, 2017
Priority date	Nov 26, 2012
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A transmitter is coupled to a command and address (CA) bus. The transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and a second swing mode. The transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, initiate calibration of the master device to send commands over the CA bus in the second swing mode, and to send a second command over the CA bus via the pins while in the second swing mode.

First claim

What is claimed is:

1. A method comprising:
sending, by a master device, commands on a command and address (CA) bus while the CA bus is in a first swing mode, wherein the master device comprises dual-mode support send the commands over the CA bus in a first swing mode and additional commands over the CA bus in a second swing mode, wherein the CA bus utilizes a first voltage reference in the first swing mode;
sending a command to initiate calibration of a second voltage reference for sending the additional commands over the CA bus in the second swing mode, wherein the second voltage reference is based on an external voltage reference and the second voltage reference is lower in voltage than the first voltage reference; and
sending, by the master device, the additional commands on the CA bus while the CA bus is in the second swing mode.

2. The method of claim 1 , wherein sending the commands on the CA bus comprises sending the commands to a slave device during startup in the first swing mode.

3. The method of claim 2 , wherein the master device is a memory controller and the slave device is a dynamic random access memory (DRAM) device.

4. The method of claim 1 , further comprising communicating data on a data bus coupled to the master device.

5. The method of claim 1 , further comprising communicating data over a data bus at the second voltage reference in the second swing mode.

6. The method of claim 1 , further comprising communicating data over a data bus at the second voltage reference in both the first swing mode and the second swing mode.

7. A method comprising:
booting up a memory controller in a first swing mode of operation, the memory controller being coupled to a command and address (CA) bus and a data bus;
providing an external voltage reference (Vref) on the CA bus;
sending a first command on the CA bus from the memory controller to transition the CA bus to a second swing mode of operation, wherein the first command is sent over the CA bus using a first Vref in the first swing mode of operation;
while the CA bus is in the second swing mode, sending a second command from the memory controller to initiate calibration of a dynamic random access memory (DRAM) device to receive commands over the CA bus using a second Vref, wherein the second Vref is based on the external Vref and the second Vref is lower in voltage than the first Vref; and
while the CA bus is in the second swing mode and after sending the second command to initiate calibration of the second Vref, sending a third command from the memory controller on the CA bus, wherein the third command is sent over the CA bus using the second Vref in the second swing mode of operation.

8. The method of claim 7 , further comprising communicating data over the data bus in the second swing mode of operation.

9. The method of claim 7 , wherein the booting up comprises communicating data over the CA bus in a default startup condition using the first Vref.

10. The method of claim 9 , further comprising generating the first Vref for the CA bus when in the first swing mode using a resister divider and a voltage supply (Vdd).

11. The method of claim 7 , further comprising:
encoding the first command, wherein the first command is a first calibration command to calibrate an initial offset and an initial Vref for the CA bus in the second swing mode; and
encoding the second command, wherein the second command is a second calibration command to disable command decoding and to initiate the calibrating the Vref.

12. The method of claim 7 , wherein the booting up the memory controller in the first swing mode comprises booting up the DRAM device in a first data rate mode for the data bus, and wherein, in the second swing mode, the transitioning the data bus to a second data rate mode that has higher data rates than the first data rate mode.

13. A master device comprising:
pins configurable to couple to a command and address (CA) bus; and
a transmitter coupled to the pins, wherein the transmitter is configurable with dual-mode support to send commands over the CA bus in a first swing mode and additional commands over the CA bus in a second swing mode, wherein the transmitter uses a first voltage reference in the first swing mode, wherein the transmitter is configurable to send a first command over the CA bus via the pins while in the first swing mode, send a second command to initiate calibration of a second voltage reference used to send the additional commands over the CA bus in the second swing mode, wherein the second voltage reference is based on an external voltage reference and the second reference voltage is lower in voltage than the first voltage reference, and wherein the transmitter is configurable to send a third command over the CA bus via the pins while in the second swing mode.

14. The master device of claim 13 , wherein the transmitter is configurable to send the first command and the third command to a slave device.

15. The master device of claim 14 , wherein the slave device comprises a memory device and the master device comprises a memory controller.

16. The master device of claim 13 , wherein the transmitter comprises a first selection circuit configurable to select between a default voltage reference (Vref) for the first voltage reference in the first swing mode and an internal Vref, generated by a voltage generation circuit, for the second voltage reference in the second swing mode.

17. The master device of claim 16 , further comprising a resistive voltage divider configurable to generate the default Vref.

18. The master device of claim 13 , wherein the transmitter is configurable to communicate data on a data bus in a high-swing, low-data rate mode and a low-swing, high-data rate mode.

19. The master device of claim 13 , wherein the transmitter is configurable to communicate data on a data bus in a high-swing, high-data rate mode and a low-swing, high-data rate mode.

Assignees

• Rambus Inc

Inventors

• Venkatesan Pravin Kumar
• Gopalakrishnan Liji
• Prabhu Kashinath
• Shirasgaonkar Makarand

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• Y02D10/14

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title