Storage controller and storage device for PCIe communication optimization

Patent metadata

Field	Value
Publication number	US-12332830-B2
Application number	US-202318304839-A
Country	US
Kind code	B2
Filing date	Apr 21, 2023
Priority date	Jul 18, 2022
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A storage controller receives a first transmission preset value and a first coefficient value at a first time from outside, at a phase 3 stage of a PCIe link training and equalization, checks whether the first transmission preset value and the first coefficient value are optimal with reference to a database, transmits signals corresponding to the first transmission preset value and the first coefficient value to the outside when the first transmission preset value and the first coefficient value are determined to be optimal and transmits signals corresponding to a second transmission preset value and a second coefficient value from the database, which are different from the first transmission preset value and the first coefficient value and optimal for the phase 3 stage of the PCIe link training and equalization, to the outside when the first transmission preset value and the first coefficient value are determined not to be optimal.

First claim

What is claimed is:

1. A storage controller comprising:
a link manager comprising:
a first logic circuit that receives a first transmission preset value and a first coefficient value associated with a first port at from a host, at a phase 3 stage of a Peripheral Component Interconnect Express (PCIe) link training and equalization; and
a second logic circuit that determines the first transmission preset value and the first coefficient value are optimal for the phase 3 stage of the PCIe link training and equalization when the first transmission preset value and the first coefficient value are present as a pair in a database and the pair has been recorded a maximum number of times for the first port,
wherein when the first transmission preset value and the first coefficient value are determined to be optimal for the phase 3 stage of the PCIe link training and equalization, the second logic circuit transmits a signal including the first transmission preset value and the first coefficient value to the host, and
when the first transmission preset value and the first coefficient value are determined not to be optimal for the phase 3 stage of the PCIe link training and equalization, the second logic circuit transmits a signal including a second transmission preset value and a second coefficient value, which are different from the first transmission preset value and the first coefficient value, to the host.

2. The storage controller of claim 1 , further comprising: a buffer memory, wherein the database is stored in the buffer memory.

3. The storage controller of claim 2 , wherein the buffer memory is a volatile memory.

4. The storage controller of claim 1 , wherein the second logic circuit further includes a calculator, with reference to the database, for the first port and a first lane to which the first transmission preset value and the first coefficient value are transmitted, the calculator checks transmission preset values and coefficient values recorded for the first port and the first lane, and the calculator sets the transmission preset value and the coefficient value recorded the maximum number of times for the first port and the first lane to the second transmission preset value and the second coefficient value.

5. The storage controller of claim 1 , wherein the link manager further includes a third logic circuit that determines a booting type prior to a first time during which the first logic circuit receives the first transmission preset value and the first coefficient value.

6. The storage controller of claim 5 , wherein the third logic circuit determines the booting type to be a warm boot, when a PERST #Asserted signal is received prior to a defined time, from a time at which a PERST #Deasserted signal is received from the host, after booting prior to the first time, and the third logic circuit determines the booting type to be a cold boot, when the PERST-#Asserted signal is not received from the host prior to the defined time, from the time at which the PERST-#Deasserted signal is received, after booting prior to the first time.

7. The storage controller of claim 6 , wherein the third logic circuit resets the database when the cold boot occurs.

8. A storage device comprising:
a storage controller, wherein the storage controller includes a link manager comprising:
a first logic circuit which receives a first transmission preset value and a first coefficient value associated with a first port from a host, at a phase 3 stage of a Peripheral Component Interconnect Express (PCIe) link training and equalization; and
a second logic circuit which determines the first transmission preset value and the first coefficient value are optimal for the phase 3 stage of the PCIe link training and equalization when the first transmission preset value and the first coefficient value are present as a pair in database and the pair has been recorded a maximum number of times for the first port,
wherein when the first transmission preset value and the first coefficient value are determined to be optimal for the phase 3 stage of the PCIe link training and equalization, the second logic circuit transmits a signal including the first transmission preset value and the first coefficient value to the host, and
when the first transmission preset value and the first coefficient value are determined not to optimal for the phase 3 stage of the PCIe link training and equalization, the second logic circuit transmits a signal including a second transmission preset value and a second coefficient value, which are different from the first transmission preset value and the first coefficient value, to the host.

9. The storage device of claim 8 , wherein the storage controller further includes a buffer memory and the database is stored in the buffer memory.

10. The storage device of claim 9 , wherein the buffer memory is a volatile memory.

11. The storage device of claim 8 , wherein the second logic circuit further includes a calculator, with reference to the database, for the first port and a first lane to which the first transmission preset value and the first coefficient value are transmitted, the calculator checks transmission preset values and coefficient values recorded for the first port and the first lane, and the calculator sets the transmission preset value and the coefficient value recorded the maximum number of times for the first port and the first lane to the second transmission preset value and the second coefficient value.

12. The storage device of claim 8 , wherein the link manager further includes a third logic circuit that determines a booting type prior to a first time during which the first logic circuit receives the first transmission preset value and the first coefficient value.

13. The storage device of claim 12 , wherein the third logic circuit determines the booting type to be a warm boot, when a PERST #Asserted signal is received prior to a defined time, from a time at which a PERST #Deasserted signal is received from the host, after booting prior to the first time, and the third logic circuit determines the booting type to be a cold boot, when the PERST_Asserted signal is not received from the outside prior to the defined time, from the time at which the PERST_Deasserted signal is received, after booting prior to the first time.

14. The storage device of claim 13 , wherein the third logic circuit resets the database when the cold boot occurs.

15. The storage device of claim 8 , further comprising: a non-volatile memory device, wherein the database is stored in the non-volatile memory device.

16. A storage system comprising:
a host device; and
a storage device which receives a first transmission preset value and a first coefficient value associated with a first port from the host device at a phase 3 stage of a PCIe link training and equalization, wherein the storage device includes a storage controller, the storage controller includes a link manager comprising:
a first logic circuit; and
a second logic circuit which determines the first transmission preset value and the first coefficient value are optimal for the phase 3 stage of the PCIe link training and equalization when the first transmission preset value and the first coefficient value are present as a pair in a database and the pair has been recorded a maximum number of times for the first port,
wherein when the first transmission preset value and the first coefficient value are determined to optimal for the phase 3 stage of the PCIe link training and equalization, the second logic circuit transmits a signal including the first transmission preset val

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Jae Hwan
• Yoo Hyun Jung
• Lee Byung Yo
• Jun Walter
• Kim Ji-Hoon
• Lee Jung Woo

Classifications

• G06F2213/0026

  PCI express · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0614 Primary

  Improving the reliability of storage systems · CPC title