Apparatus, system, and method for improving equalization with a hardware driven algorithm

Patent metadata

Field	Value
Publication number	US-9645965-B2
Application number	US-201313840104-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 15, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component.

First claim

What is claimed is:

1. A system, comprising:
in response to a first component and a link partner component of the first component undergoing equalization, the first component is to communicate a first set of data to the link partner component, the first component comprises:
at least one receiver to receive a first set of equalization data, the first set of equalization data includes a full swing value (FS) and a low frequency value (LF);
coefficient storage coupled to the at least one receiver to store the first set of equalization data;
coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data, the first set of coefficients comprise: a first coefficient value (C 1 ), a second coefficient value (C 2 ), and a third coefficient value (C 3 );
the coefficient logic is configured to generate C 1 , C 2 , C 3 such that:
if [FS+LF] is even and divisible by 4, then C 1 and C 2 are equal to the absolute value of [(FS−LF)/4], and C 3 is equal to [FS−C 1 −C 2 ];
otherwise if [FS+LF] is even but not divisible by 4, then the C 1 equals Ceiling[(FS−LF)/4], C 2 equals a Floor[(FS−LF)/4], and C 3 equals [FS−C 1 −C 2 ];
if [FS+LF] is odd and (FS−LF−1=VAL) is divisible by 4, then C 1 equals C 2 =floor[VAL/4] and C 3 =[FS−C 1 −C 2 ]; and
otherwise if [FS+LF] is odd and (FS−LF−1=VAL) is not divisible by 4, then C 1 equals Ceiling[VAL/4], C 2 =floor[VAL/4] and C 3 =[FS−C 1 −C 2 ]; and

the first component is configured to send the first set of coefficients to the link partner component.

2. The system of claim 1 , wherein the first set of coefficients includes midpoint coordinates along a maximum boost line.

3. The system of claim 1 , wherein the first component is a root complex component and the link partner component is an endpoint component.

4. The system of claim 1 , wherein the first component sends the first set of coefficients to the link partner component via a Peripheral Component Interconnect Express (PCIe) bus interface link.

5. The system of claim 1 wherein further, in response to the first component and the link partner component undergoing the equalization, the first component communicates a second set of data to the link partner component wherein the link partner component applies at least a portion of the second set of data for a transmitter set-up of the link partner component.

6. The system of claim 1 , wherein the generated first set of coefficients includes a precursor component, cursor component, and post-cursor component.

7. A method, comprising:
communicating a first set of data to a first component from a link partner component along at least one channel of a communications link, the first set of data includes a full swing value (FS) and a low frequency value (LF);
wherein the full swing value and the low frequency value is stored in at least one register of the first component;
determining, by the first component, a first set of coefficients from the full swing value and the low frequency value, the first set of coefficients comprises a first coefficient value (C 1 ), a second coefficient value (C 2 ), and a third coefficient value (C 3 );
said determining of the first set of coefficients comprises:
if [FS+LF] is even and divisible by 4, then the C 1 and C 2 are equal to the absolute value of [(FS−LF)/4], and C 3 is equal to [FS−C 1 −C 2 ];
otherwise if [FS+LF] is even but not divisible by 4, then C 1 equals Ceiling[(FS−LF)/4], C 2 equals a Floor[(FS−LF)/4], and C 3 equals [FS−C 1 −C 2 ];
if [FS+LF] is odd and (FS−LF−1=VAL) is divisible by 4, then C 1 equals C 2 =floor[VAL/4] and C 3 =[FS−C 1 −C 2 ];
otherwise if [FS+LF] is odd and (FS−LF−1=VAL) is not divisible by 4, then C 1 equals Ceiling[VAL/4], C 2 =floor[VAL/4] and C 3 =[FS−C 1 −C 2 ];

storing the determined first set of coefficients in at least one register of the first component; and
applying the determined first set of coefficients sent by the first component in order to set-up a transmitter component of the link partner component.

8. The method of claim 7 , wherein the first set of data includes a first set of preset values which includes a second set of coefficients to set-up a transmitter component of the link partner component and a first set of preset hints which includes a second set of coefficients to set-up a receiver component of the link partner component.

9. The method of claim 7 , wherein the determined first set of coefficients includes at least one of a pre-cursor coefficient, cursor coefficient, or post-cursor coefficient.

10. The method of claim 7 , wherein the first set of coefficients applied to the transmitter component of the link partner component enables the link partner component to transmit data to the first component with a bit error rate of less than or equal to one error per every 10 12 bits.

11. The method of claim 7 , wherein the determined first set of coefficients are applied to the transmitter component of the link partner component during Phase 3 of a PCI Gen 3 link training and equalization procedure.

12. An system, comprising:
a downstream port which in response to undergoing a link training and equalization procedure, receives a first ordered set from an upstream port;
the upstream port includes a transmitter component to transmit data to the downstream port;
the downstream port includes:
a receiver component to receive data from the upstream port, the upstream port and the downstream port are link partners;
wherein the first ordered set includes a full swing value (FS) and a low frequency value (LF) associated with the upstream port;
coefficient logic configured to determine a first set of coefficients from the full swing value and the low frequency value of the first ordered set, such that:
if [FS+LF] is even and divisible by 4, then the C 1 and C 2 are equal to the absolute value of [(FS−LF)/4], and C 3 is equal to [FS−C 1 −C 2 ];
otherwise if [FS+LF] is even but not divisible by 4, then C 1 equals Ceiling[(FS−LF)/4], C 2 equals a Floor[(FS−LF)/4], and C 3 equals [FS−C 1 −C 2 ];
if [FS+LF] is odd and (FS−LF−1=VAL) is divisible by 4, then C 1 equals C 2 =floor[VAL/4] and C 3 =[FS−C 1 −C 2 ];
otherwise if [FS+LF] is odd and (FS−LF−1=VAL) is not divisible by 4, then C 1 equals Ceiling[VAL/4], C 2 =floor[VAL/4] and C 3 =[FS−C 1 −C 2 ];

at least one configuration register to store the determined first set of coefficients; and

wherein the upstream port applies the determined first set of coefficients sent by the downstream port in order to set-up the transmitter component of the upstream port.

13. The system of claim 12 , wherein the upstream port further includes a receiver which receives the determined first set of coefficients from the downstream port.

14. The system of claim 12 , wherein the determined first set of coefficients are stored in a single configuration register.

15. The system of claim 12 , wherein the at least one configuration register are implemented as flip-flop storage elements.

16. The system of claim 12 , wherein data within the at least one configuration register provides a status of the upstream port.

17. The system of claim 12 , wherein the upstream port is coupled to a touch enabled display device.

18. A link training and equalization procedure for devices coupled to a bus interface link, comprising:
communicating a set of transmitter preset values and a set of receiver hints from a first component to a link partner component and from the link partner component to the first component;
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Assignees

• Das Sharma Debendra
• Gadey Naga Venkata Kanaka Lakshimi Siva Prasad
• Jayaprakash Bharadwaj Prahladachar
• Intel Corp

Inventors

• Das Sharma Debendra
• Gadey Naga Venkata Kanaka Lakshimi Siva Prasad
• Jayaprakash Bharadwaj Prahladachar

Classifications

• H04L2025/03808

  Transmission of equaliser coefficients · CPC title

• G06F17/11 Primary

  for solving equations {, e.g. nonlinear equations, general mathematical optimization problems (optimization specially adapted for a specific administrative, business or logistic context G06Q10/04)} · CPC title

• H04L2025/03802

  Signalling on the reverse channel · CPC title

• H04L5/1438

  Negotiation of transmission parameters prior to communication (modified according to link quality H04L1/0001) · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title