Adaptive interface storage device with multiple storage protocols including NVME and NVME over fabrics storage devices

Patent metadata

Field	Value
Publication number	US-10901927-B2
Application number	US-201916696649-A
Country	US
Kind code	B2
Filing date	Nov 26, 2019
Priority date	Mar 9, 2018
Publication date	Jan 26, 2021
Grant date	Jan 26, 2021

Abstract

An adaptive interface storage device. In some embodiments, the adaptive interface storage device includes: a rear storage interface connector; an adaptable circuit connected to the rear storage interface connector; a first multiplexer, connected to the adaptable circuit; and a front storage interface connector, connected to the first multiplexer. The adaptive interface storage device may be configured to operate in a first state or in a second state. The adaptive interface storage device may be configured: in the first state, to present a device side storage interface according to a first storage protocol at the front storage interface connector, and in the second state, to present a device side storage interface according to a second storage protocol, different from the first storage protocol, at the front storage interface connector.

First claim

What is claimed is:

1. A device comprising:
a first connector;
a first circuit connected to the first connector;
a second circuit, connected to the first circuit; and
a second connector, connected to the second circuit,
the device being configured to operate in a first state or in a second state,
the device being configured:
in the first state, to present a first interface according to a first protocol at the second connector, and
in the second state, to present a second interface according to a second protocol, different from the first protocol, at the second connector,

wherein the second protocol is NVMe over Fabrics.

2. The device of claim 1 , wherein:
the first circuit comprises a first endpoint and a second endpoint, and
the second circuit is a first multiplexer comprising:
a first multiplexer channel having a first multiplexer channel common port connected to the second connector and
a second multiplexer channel having:
a second multiplexer channel common port connected to the second connector,
a second multiplexer channel first selectable port connected to the first endpoint, and
a second multiplexer channel second selectable port connected to the second endpoint.

3. The device of claim 2 , wherein the first multiplexer channel has a first multiplexer channel first selectable port connected to the first endpoint.

4. The device of claim 3 , wherein:
the first multiplexer channel has a first multiplexer channel second selectable port, the first multiplexer channel second selectable port being not connected,
in the first state, the first multiplexer channel first selectable port is selected, and
in the second state, the first multiplexer channel first selectable port is selected.

5. The device of claim 2 , wherein the first protocol is NMVe.

6. The device of claim 2 , wherein the first circuit is connected to a first plurality of conductors of the second connector, and the first circuit is configured, in the second state, to present an Ethernet interface at the first plurality of conductors.

7. The device of claim 6 , wherein the second protocol is NVMe over Fabrics, over the Ethernet interface.

8. The device of claim 2 , wherein, in the first state, the second multiplexer channel first selectable port is selected.

9. The device of claim 8 , wherein, in the second state, the second multiplexer channel second selectable port is selected.

10. The device of claim 9 , wherein the device is further configured, in the second state, to present a first control plane interface at the second connector.

11. The device of claim 2 , wherein:
the first endpoint is a four-lane endpoint,
the second endpoint is a four-lane endpoint, and
the second multiplexer channel common port has two input lanes and two output lanes.

12. The device of claim 1 , wherein the first circuit is a programmable adaptable circuit, having a configuration port, and being configured, at system startup, to load a bitfile through the configuration port.

13. The device of claim 12 , wherein the second circuit is a first multiplexer, the device further comprising:
a first bitfile memory;
a second bitfile memory; and
a second multiplexer,
the second multiplexer having:
a second multiplexer common port connected to the configuration port;
a second multiplexer first selectable port connected to the first bitfile memory; and
a second multiplexer second selectable port connected to the second bitfile memory.

14. The device of claim 13 , wherein,
in the first state, the second multiplexer first selectable port is selected, and
in the second state, the second multiplexer second selectable port is selected.

15. The device of claim 1 , wherein the second connector is a U.2 connector.

16. The device of claim 1 , further comprising a state control input configured to receive a signal for selecting between the first state and the second state.

17. The device of claim 16 , wherein the second connector is a U.2 connector having an E6 pin, and the state control input is the E6 pin.

18. A device, comprising:
a second connector; and
persistent storage,
the device being configured to operate in a first state or in a second state, the device being configured:
in the first state, to present a device side NVMe storage interface at the second connector, and
in the second state, to present a device side NVMe over Fabrics storage interface at the second connector.

19. A system, comprising:
a chassis; and
a device,
the device comprising:
a first connector;
a first circuit connected to the first connector; and
a second circuit, connected to the first circuit,
a second connector, connected to the second circuit,

the device being configured to operate in a first state or in a second state,
the device being configured:
in the first state, to present a first interface according to a first protocol at the second connector, and
in the second state, to present a second interface according to a second protocol, different from the first protocol, at the second connector,

wherein the second protocol is NVMe over Fabrics.

20. The system of claim 19 , wherein:
the device further comprises a state control input configured to receive a signal for selecting between the first state, and the second state, and
the chassis is hard-wired to supply to the state control input a signal selecting the first state.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Fischer Stephen G
• Olarig Sompong Paul

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F3/0685

  Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays · CPC title