ESD protection decoupled from diffusion

Patent metadata

Field	Value
Publication number	US-12328946-B2
Application number	US-202017133595-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Dec 23, 2020
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate, wherein a transistor device is provided on the semiconductor substrate;
a stack of routing layers over the semiconductor substrate; and
a diode in the stack of routing layers, wherein the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device; and wherein the diode comprises:
a first electrode;
a semiconductor region over the first electrode; and
a second electrode over the semiconductor region.

2. The semiconductor device of claim 1 , wherein the transistor device is a non-planar transistor.

3. The semiconductor device of claim 2 , wherein the transistor device is a gate-all-around (GAA) transistor.

4. The semiconductor device of claim 1 , wherein a first interface between the first electrode and the semiconductor region is a Schottky contact, and wherein a second interface between the second electrode and the semiconductor region is an ohmic contact.

5. The semiconductor device of claim 1 , wherein the semiconductor region comprises:
a first layer with a first material composition; and
a second layer with a second material composition that is different than the first material composition.

6. The semiconductor device of claim 5 , wherein the first layer comprises an insulating oxide material, and the second layer comprises a conducting oxide.

7. The semiconductor device of claim 1 , wherein the semiconductor region comprises:
a layer with a compositional gradient through a thickness of the semiconductor region between the first electrode and the second electrode.

8. The semiconductor device of claim 7 , wherein the compositional gradient comprises an insulating oxide material at a first end and a conducting oxide at a second end.

9. The semiconductor device of claim 1 , wherein the diode is a Schottky diode.

10. A method of forming a semiconductor device with electrostatic discharge (ESD) protection, comprising:
forming a non-planar transistor on a semiconductor layer;
forming a stack of routing layers over the semiconductor layer; and
forming a diode in the stack of routing layers, wherein the diode is configured to provide ESD protection to the non-planar transistor, and wherein forming the diode comprises:
forming a first electrode;
forming a semiconductor region over the first electrode; and
forming a second electrode over the semiconductor region, wherein a first interface between the semiconductor region and the first electrode is a Schottky contact, and wherein a second interface between the semiconductor region and the second electrode is an ohmic contact.

11. The method of claim 10 , wherein the semiconductor region comprises a compositional gradient between the first interface and the second interface.

12. The method of claim 11 , wherein the compositional gradient is formed using binary oxide targets in a physical vapor deposition process.

13. The method of claim 11 , wherein the compositional gradient is formed with a process comprising:
implanting a surface of the semiconductor region with dopants; and
annealing the semiconductor region to diffuse the dopants into the semiconductor region.

14. The method of claim 11 , wherein the compositional gradient is formed with a process comprising:
forming a sacrificial layer over the semiconductor region;
annealing the semiconductor region to drive diffusion of the sacrificial layer into the semiconductor region; and
removing the sacrificial layer.

15. The method of claim 11 , wherein the compositional gradient starts at the first interface with a first material composition comprising an insulating oxide material, and the compositional gradient ends at the second interface with a second material composition comprising a conductive oxide material.

16. An electronic system, comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises:
a semiconductor substrate, wherein a transistor device is provided on the semiconductor substrate;
a stack of routing layers over the semiconductor substrate; and
a diode in the stack of routing layers, wherein the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device, wherein the diode comprises:
a first electrode;
a semiconductor region over the first electrode; and
a second electrode over the semiconductor region.

17. The electronic system of claim 16 , wherein a first interface between the first electrode and the semiconductor region is a Schottky contact, and wherein a second interface between the second electrode and the semiconductor region is an ohmic contact.

Assignees

• Intel Corp

Inventors

• Alaan Urusa
• Sharma Abhishek A
• Kuo Charles C
• Orr Benjamin
• THOMSON Nicholas
• Kar Ayan
• Sen Gupta Arnab
• Oguz Kaan
• Doyle Brian S
• Majhi Prashant
• Le Van H
• Karpov Elijah V

Classifications

• H10D62/875

  being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874) · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• H10D8/60

  Schottky-barrier diodes · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D89/931

  characterised by the dispositions of the protective arrangements · CPC title