Integration of 2T-NC for memory and logic applications

Patent metadata

Field	Value
Publication number	US-12328878-B1
Application number	US-202217655432-A
Country	US
Kind code	B1
Filing date	Mar 18, 2022
Priority date	Mar 15, 2022
Publication date	Jun 10, 2025
Grant date	Jun 10, 2025

Abstract

A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.

First claim

What is claimed is:

1. A system comprising:
a processor comprising a plurality of transistors in a first level, wherein individual ones of the plurality of transistors comprise:
a source;
a drain;
a gate between the source and the drain;
a drain contact coupled with the drain; and
a gate contact coupled with the gate;

a bridge structure connected between the gate contact of a first transistor in the plurality of transistors to the drain contact of a second transistor in the plurality of transistors;
a bit-cell above the first transistor and the second transistor, the bit-cell comprising:
a conductive interconnect within a first dielectric in a second level, wherein the conductive interconnect is electrically coupled with the bridge structure; and
a third level above the second level, the third level comprising:
an electrode structure on the conductive interconnect, the electrode structure comprising:
a first conductive hydrogen barrier layer; and
a first conductive fill material on the first conductive hydrogen barrier layer, wherein the electrode structure comprises a first lateral thickness;

a plurality of memory devices above the electrode structure, wherein individual ones of the plurality of memory devices comprise:
a bottom electrode;
a top electrode; and
a nonlinear polar dielectric between the top electrode and the bottom electrode;
an insulative hydrogen barrier layer encapsulating on at least a sidewall of the individual ones of the plurality of memory devices;
a plate electrode coupled between the plurality of memory devices and the electrode structure, wherein the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices; and
a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices, and
wherein the individual ones of the plurality of via electrodes comprise:
a second conductive hydrogen barrier layer comprising a lateral portion and substantially vertical portions connected to two ends of the lateral portion; and
a second conductive fill material on the lateral portion and between the substantially vertical portions.

2. The system of claim 1 , wherein the plate electrode extends beyond a perimeter of the individual ones of the plurality of transistors.

3. The system of claim 1 , wherein the plate electrode comprises a first thickness under the individual ones of the plurality of memory devices and a second thickness away from the individual ones of the plurality of memory devices.

4. The system of claim 3 , wherein the insulative hydrogen barrier layer further comprises:
a first portion that is substantially aligned with a third perimeter of the plate electrode; and
a second portion between the individual ones of the plurality of memory devices and a third portion on the individual ones of the plurality of memory devices.

5. The system of claim 1 further comprising a conductive electrode in the first level, wherein the conductive electrode is directly between the bridge structure and the conductive interconnect, and wherein the bridge structure comprises a conductive material.

6. The system of claim 1 , wherein the electrode structure is directly between a memory device in the plurality of memory devices and the conductive interconnect.

7. The system of claim 1 , wherein the plate electrode comprises:
a third portion that extends along a first direction on a first plane;
a fourth portion that extends parallel to the first direction, the fourth portion on a second plane, the second plane behind the first plane; and
a fifth portion that extends orthogonally from the third portion to the fourth portion.

8. The system of claim 7 , wherein the third portion is connected to a first midpoint of the third portion to a second midpoint of the fourth portion, and wherein the plate electrode comprises:
a first pair of memory devices in the plurality of memory devices on the third portion;
a second pair of memory devices in the plurality of memory devices on the fourth portion; and
at least one memory device in the plurality of memory devices on the fifth portion.

9. The system of claim 1 , wherein the individual ones of the plurality of memory devices comprise a circular, an elliptical, or a rectangular plan view profile.

10. The system of claim 1 , wherein the nonlinear polar dielectric comprises one of:
bismuth ferrite (BFO) or BFO with a first doping material wherein the first doping material is one of lanthanum or elements from lanthanide series of periodic table;
lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb;
a relaxor ferroelectric material which includes one of lead: magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST);
a perovskite material which includes one of: BaTiO 3 , PbTiO 3 , KNbO 3 , or NaTaO 3 ; hexagonal ferroelectric which includes one of: YMnO 3 , or LuFeO 3 ; hexagonal ferroelectrics of a type h-RMnO 3 , where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y);
hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides or their alloyed oxides; hafnium oxides as Hf (1−x) E x O y , where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively; Al (1−x) Sc (x) N, Ga (1−x) Sc (x) N, Al (1−x) Y (x) N or Al (1−x−y) Mg (x) Nb (y) N, wherein x and y are third and fourth fractions, respectively;
y doped HfO 2 , where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; or
niobate type compounds LiNbO 3 , LiTaO 3 , lithium iron tantalum oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or
an improper ferroelectric material which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 and 100; or

a paraelectric material comprising SrTiO 3 , Ba (x) Sr (y) TiO 3 (where x is −0.05, and y is 0.95), HfZrO 2 , Hf—Si—O, La-substituted PbTiO 3 , or a PMN-PT based relaxor ferroelectrics; and
wherein the top electrode and the bottom electrode comprise one of La—Sr—CoO3, SrRuO3, La—Sr—MnO 3 , YBa 2 Cu 3 O 7 , Bi 2 Sr 2 CaCu 2 O 8 , or LaNiO 3 .

11. The system of claim 1 , wherein the first conductive hydrogen barrier layer is between the conductive interconnect and the first conductive fill material, and wherein the first conductive hydrogen barrier layer and the second conductive hydrogen barrier layer comprise TiAlN, with greater than 30 atomic percent AlN, TaN with greater than 30 atomic percent N 2 , TiSiN with greater than 20 atomic percent SiN, TaC, TiC, WC, WN, carbonitrides of Ta, Ti or W, TiO, Ti 2 O, WO 3 , SnO 2 , ITO, IGZO, ZO, or METGLAS series of alloys.

12. The system of claim 1 , wherein the conductive interconnect extends longitudinally along a first direction, orthogonal to a second direction from the first transistor to the second transistor, and wherein the plate electrode extends longitudinally along a third direction orthogonal to the first direction, but parallel to the second direction.

13. A syst

Assignees

• Kepler Computing Inc

Inventors

• Sato Noriyuki
• Gosavi Tanay
• Rios Rafael
• Mathuriya Amrita
• Mukherjee Niloy
• Manfrini Mauricio
• Dokania Rajeev Kumar
• Rathi Somilkumar J
• Manipatruni Sasikanth

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title

• H10D1/711

  having non-planar surfaces, e.g. formed by texturisation · CPC title

• H10N79/00

  Integrated devices, or assemblies of multiple devices, comprising at least one solid-state element covered by group H10N70/00 (ReRAM devices H10B63/00; PCRAM devices H10B63/10) · CPC title